FreeCalypso > hg > freecalypso-tools

annotate target-utils/lunadrv/formike.c @ 937:06f96627ac9a

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rvinterf TM log: decode TMFFS2 commands
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 24 May 2023 04:25:47 +0000
parents 21e0e6492cda
children
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db9a8e88e63f target-utils lunadrv program written, compiles
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1 #include "types.h"
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2 #include "luna.h"
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3
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4 /*
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5 * ILI9225G register init for Formike KWH020ST23-F01 LCD. This initialization
21e0e6492cda lunadrv: add init-kwh for KWH020ST23-F01 LCD
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6 * is almost exactly the same as for our previous HaoRan HT020K1QC36S LCD,
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7 * except for a different VCOMH setting in register 0x14. Our Formike sales
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8 * engineer confirmed that the new register setting is required for the new LCD.
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9 */
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10
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11 init_formike()
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12 {
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13 /* reset pulse */
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14 CNTL_RST_REG |= EXT_RESET;
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15 wait_ARM_cycles(DELAY_1MS * 10);
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16 CNTL_RST_REG &= ~EXT_RESET;
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17 wait_ARM_cycles(DELAY_1MS * 50);
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18 /* start register init */
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19 LCD_REG_WR(0x0001, 0x011c); // set SS and NL bit
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20 LCD_REG_WR(0x0002, 0x0100); // set 1 line inversion
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21 LCD_REG_WR(0x0003, 0x1030); // set GRAM write direction and BGR=1.
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22 LCD_REG_WR(0x0008, 0x0808); // set BP and FP
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23 LCD_REG_WR(0x000F, 0x0901); // Set frame rate
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24 wait_ARM_cycles(DELAY_1MS * 10);
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25 LCD_REG_WR(0x0010, 0x0000); // Set SAP,DSTB,STB
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26 LCD_REG_WR(0x0011, 0x1B41); // Set APON,PON,AON,VCI1EN,VC
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27 wait_ARM_cycles(DELAY_1MS * 50);
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28 LCD_REG_WR(0x0012, 0x200E); // Internal reference voltage= Vci;
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29 LCD_REG_WR(0x0013, 0x0052); // Set GVDD
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30 LCD_REG_WR(0x0014, 0x535C); // new VCOMH setting for KWH020ST23-F01
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31 //------------- Set GRAM area ------------------//
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32 LCD_REG_WR(0x0030, 0x0000);
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33 LCD_REG_WR(0x0031, 0x00DB);
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34 LCD_REG_WR(0x0032, 0x0000);
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35 LCD_REG_WR(0x0033, 0x0000);
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36 LCD_REG_WR(0x0034, 0x00DB);
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37 LCD_REG_WR(0x0035, 0x0000);
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38 LCD_REG_WR(0x0036, 0x00AF);
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39 LCD_REG_WR(0x0037, 0x0000);
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40 LCD_REG_WR(0x0038, 0x00DB);
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41 LCD_REG_WR(0x0039, 0x0000);
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42 // ----------- Adjust the Gamma Curve ----------//
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43 LCD_REG_WR(0x0050, 0x0000);
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44 LCD_REG_WR(0x0051, 0x0705);
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45 LCD_REG_WR(0x0052, 0x0C0A);
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46 LCD_REG_WR(0x0053, 0x0401);
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47 LCD_REG_WR(0x0054, 0x040C);
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48 LCD_REG_WR(0x0055, 0x0608);
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49 LCD_REG_WR(0x0056, 0x0000);
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50 LCD_REG_WR(0x0057, 0x0104);
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51 LCD_REG_WR(0x0058, 0x0E06);
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52 LCD_REG_WR(0x0059, 0x060E);
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53 wait_ARM_cycles(DELAY_1MS * 50);
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54 LCD_REG_WR(0x0007, 0x1017);
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55 return(0);
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56 }