FreeCalypso > hg > freecalypso-tools

annotate target-utils/c139explore/uwire.c @ 416:30f6d1c32c6f

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doc/Flash-boot-defect article removed (no longer relevant) This article is no longer relevant because the issue in question only affected one (1) defective FCDEV3B board which was not and never will be sold.
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 26 Oct 2018 07:11:08 +0000
parents e7502631a0f9
children
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1 /* Driver for uWire Master Controller inside TI Calypso */
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2 /* lifted from OsmocomBB and ported to FreeCalypso target-utils environment */
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3
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4 /* (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
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5 *
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6 * All Rights Reserved
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7 *
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8 * This program is free software; you can redistribute it and/or modify
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9 * it under the terms of the GNU General Public License as published by
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10 * the Free Software Foundation; either version 2 of the License, or
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11 * (at your option) any later version.
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12 *
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13 * This program is distributed in the hope that it will be useful,
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 * GNU General Public License for more details.
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17 *
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18 * You should have received a copy of the GNU General Public License along
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19 * with this program; if not, write to the Free Software Foundation, Inc.,
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20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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21 *
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22 */
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23
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24 #include "types.h"
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25
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26 struct uwire_regs {
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27 u16 reg_data;
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28 u16 reg_csr;
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29 u16 reg_sr1;
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30 u16 reg_sr2;
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31 u16 reg_sr3;
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32 };
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33
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34 #define UWIRE_REGS (*(volatile struct uwire_regs *) 0xFFFE4000)
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35
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36 #define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0)
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37 #define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5)
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38 #define UWIRE_CSR_IDX(n) (((n) & 3) << 10)
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39 #define UWIRE_CSR_CS_CMD (1 << 12)
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40 #define UWIRE_CSR_START (1 << 13)
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41 #define UWIRE_CSR_CSRB (1 << 14)
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42 #define UWIRE_CSR_RDRB (1 << 15)
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43
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44 #define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */
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45 #define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */
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46 #define UWIRE_CSn_CS_LVL (1 << 2)
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47 #define UWIRE_CSn_FRQ_DIV2 (0 << 3)
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48 #define UWIRE_CSn_FRQ_DIV4 (1 << 3)
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49 #define UWIRE_CSn_FRQ_DIV8 (2 << 3)
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50 #define UWIRE_CSn_CKH
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51
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52 #define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0)
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53 #define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1)
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54
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55 #define UWIRE_SR3_CLK_EN (1 << 0)
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56 #define UWIRE_SR3_CLK_DIV2 (0 << 1)
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57 #define UWIRE_SR3_CLK_DIV4 (1 << 1)
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58 #define UWIRE_SR3_CLK_DIV7 (2 << 1)
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59 #define UWIRE_SR3_CLK_DIV10 (3 << 1)
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60
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61 static inline void _uwire_wait(int mask, int val)
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62 {
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63 while ((UWIRE_REGS.reg_csr & mask) != val);
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64 }
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65
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66 /*
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67 * Let's try changing the chip select logic from OsmocomBB way
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68 * to the way seen in TI's R2D source.
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69 */
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70
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71 void uwire_init(void)
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72 {
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73 UWIRE_REGS.reg_sr3 = UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2;
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74 UWIRE_REGS.reg_sr1 = UWIRE_CSn_FRQ_DIV2;
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75 #if 0
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76 UWIRE_REGS.reg_sr1 = UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2;
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77 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
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78 _uwire_wait(UWIRE_CSR_CSRB, 0);
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79 #endif
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80 }
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81
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82 send_via_uwire(word)
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83 unsigned word;
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84 {
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85 #if 0
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86 /* select the chip */
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87 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
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88 _uwire_wait(UWIRE_CSR_CSRB, 0);
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89 #endif
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90
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91 UWIRE_REGS.reg_data = word << 7;
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92 UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START
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93 | UWIRE_CSR_CS_CMD;
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94 _uwire_wait(UWIRE_CSR_CSRB, 0);
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95
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96 /* unselect the chip */
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97 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | 0;
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98 #if 0
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99 _uwire_wait(UWIRE_CSR_CSRB, 0);
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100 #endif
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101
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102 return 0;
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103 }