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annotate target-utils/libc/strlen.S @ 778:3ba64341137b

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simagent: bare Tx works with extra delays
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 13 Mar 2021 19:31:53 +0000
parents 3670e7768ab6
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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95
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
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1 .text
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
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2 .code 32
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 .globl strlen
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 strlen:
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 mov r1, r0
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 1: ldrb r2, [r0], #1
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 cmn r2, #0
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 bne 1b
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 sbc r0, r0, r1
3670e7768ab6 target-utils/libc: strlen optimized assembly implementation added
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 bx lr