FreeCalypso > hg > freecalypso-tools
annotate doc/How-flash-really-works @ 1009:4a153059abbb
doc/DUART28-boot-control: update for fc-linux-patch and fc-usbser-tools
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 12 Dec 2023 06:57:11 +0000 |
parents | 39a6090a052a |
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1 How NOR flash memory really works |
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2 ================================= |
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3 |
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4 The type of flash memory used in Calypso GSM devices is formally known as NOR |
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5 flash. Most embedded software programmers and tinkerers know the fundamental |
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6 principle of how NOR flash works: any bit can be transitioned from a '1' to a |
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7 '0' at any time in any combination (an operation called programming), but the |
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8 opposite transition (from '0' to '1' bits, an operation called erasure) can only |
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9 be done on fairly large sectors - you can erase a sector and make it all 1s, |
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10 but changing bits from 0 to 1 individually or in any smaller granularity |
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11 (smaller than a sector) is impossible. |
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12 |
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13 What many "software-minded" programmers and tinkerers don't realize, however, |
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14 is that sector erasure is not an elementary or atomic operation that magically |
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15 "makes all bits 1s" in one motion. Instead it is a complex process with two or |
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16 three substeps: |
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17 |
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18 1) Before starting the physical process of erasure, one has to go through all |
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19 bits in the to-be-erased sector and make them all 0s. Any bits that are in |
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20 '1' state when the sector erase operation is commanded MUST be programmed to |
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21 '0' state before the actual erasure begins! In the language of flash chip |
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22 industry, this step is called preprogramming. In the case of flash chips |
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23 that are used in Calypso GSM devices (all known ones), this preprogramming |
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24 step is done internally by the chip, so that you as the user or software |
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25 developer are not aware of it - but it is there nonetheless. The chip does |
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26 NOT magically "wave" all bits in the sector into '1' state, instead it first |
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27 makes them all '0' internally, and only then erases. |
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28 |
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29 2) Once every bit in the sector is in '0' state, the real physics of erasure |
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30 begins. All bit cells in the sector are physically acted upon at once in |
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31 this step, and because it is a probabilistic process involving a Gaussian |
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32 distribution, all bit cells need to be in the fully programmed state before |
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33 they begin their shared journey toward the erased state. |
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34 |
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35 3) The step of preprogramming every bit to 0 prior to erasure prevents the |
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36 absolutely unacceptable condition of gross overerasure - but given the |
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37 Gaussian distribution, some bit cells may still get a little overerased. |
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38 Many (most? all? not sure) flash chips therefore implement a third internal |
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39 step before the software-visible "erase" operation is declared complete: |
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40 they go through all bit cells in the just-erased sector, check for |
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41 overerasure, and "soft-program" (move slightly to the right in the Vt |
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42 distribution) any overerased cells. This step is called post-erase |
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43 conditioning or recovery. |
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44 |
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45 The above process was originally explained to me (Mother Mychaela) some years |
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46 ago (around 2008, IIRC) by a Spansion support engineer on a conference call at |
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47 my then day job - it was a project for a customer who was big and powerful |
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48 enough to get top-tier support from chip vendors. More recently, however, some |
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49 other flash vendors have posted public documents that provide the same |
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50 explanation - here is one from Renesas/Adesto: |
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51 |
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52 https://www.freecalypso.org/pub/embedded/flash/REN_an500_APN_20210702_1.pdf |
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53 |
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54 Even though the above document was written by Renesas (or more precisely, the |
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55 part that was originally Adesto), the theory described therein applies just as |
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56 well to Intel, Spansion and Samsung flash chips that are used in Calypso GSM |
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57 devices. For anyone who wishes to know how NOR flash memory really works, I |
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58 strongly recommend reading that Renesas appnote - it is a good description. |
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59 |
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60 Additional note on terminology: describing the two states of a flash memory cell |
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61 as '0' and '1', like I did above, is only a convenience for software-minded |
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62 people. A more proper view is to think in terms of a "programmed state" and an |
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63 "erased state" for each bit cell. History and tradition are such that flash |
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64 chips return '0' on read in the programmed state and '1' in the erased state |
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65 (this tradition probably originates from the fact that the actual NV storage |
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66 element, a transistor, conducts read current in the erased state), at least for |
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67 the main flash array - however, when flash memory elements are used for |
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68 additional purposes such as write protection controls, it is best to think |
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69 natively in terms of programmed and erased states. For the latter kind of |
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70 special applications, an opposite polarity may be applied in read-bit values. |
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71 |
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72 One straightforward take-away from this theory is that flash endurance is really |
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73 about program-erase cycles, rather than number of program or number of erase |
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74 operations. Every time you give a sector erase command, every bit in that |
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75 sector cycles through the fully programmed (0) state first before becoming |
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76 erased (1), irrespective of whether or not you programmed into it on your own! |
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77 Hence every bit-cell of the affected sector always goes through a full |
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78 program-erase cycle, and all bits in a given sector are always cycled equally, |
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79 irrespective of whether they get written with mostly-0s or mostly-1s in between |
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80 erase cycles. |
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81 |
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82 Another situation where this raw physics gets exposed to the user is the case |
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83 of special-purpose non-volatile bits in flash chips outside of the main flash |
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84 memory array - for example, Persistent Protection Bits (PPBs) in some Spansion |
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85 and Samsung flash chips. While program and erase commands for the main flash |
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86 array invoke chip-internal mechanisms that take care of everything and present |
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87 a sane model of 0s and 1s to software, Spansion PL-J PPB program and erase |
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88 commands expose raw guts: there is a command that applies a raw program pulse |
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89 to a single PPB, and there is a command that applies a raw erase pulse to the |
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90 NV memory element (like a little sector of its own) that holds all PPBs. |
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91 Applying the erase pulse without preprogramming every PPB first would be very |
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92 bad (see Renesas appnote about the badness of overerasure) - hence in a seeming |
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93 paradox, one has to explicitly lock every sector before applying PPB erase |
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94 pulses that will eventually unlock everything! |
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95 |
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96 Our flash ppb-erase-all command does implement the preprogramming step before |
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97 actual erasure, and the present document (hopefully) explains why. |