FreeCalypso > hg > freecalypso-tools
annotate doc/Target-utils @ 740:5fdc241dcc44
target-utils/Makefile: lunadrv moved to install set
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 11 Oct 2020 03:08:13 +0000 |
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1 FreeCalypso target-utils suite |
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2 ============================== |
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3 |
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4 We have a suite of standalone programs and specialized code pieces that run on |
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5 the Calypso ARM7 processor, but are not regular operational phone or modem |
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6 firmware; this suite of code bits is called target-utils, maintained and |
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7 distributed together with FreeCalypso host tools. The primary reason for the |
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8 coupling between FC host tools and target-utils is that the target-utils suite |
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9 provides the loadagent target program for fc-loadtool and fc-xram host tools, |
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10 as well as compalstage code pieces needed for operating on Compal phones. |
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11 |
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12 Most programs in the target-utils suite are meant to execute out of RAM |
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13 (specifically, the Calypso chip's internal RAM or IRAM for short), loaded and |
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14 run via fc-iram or fc-compalram - they are not meant to be flashed. As of this |
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15 writing, the following run-from-RAM programs are available: |
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16 |
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17 buzplayer Player for buzzer melodies, used by fc-buzplay |
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18 c139explore Mot C139 hardware exploration program |
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19 calversion Calypso version ID tool, primarily for the DSP ROM version |
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20 dspdump Calypso DSP ROM dump tool |
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21 helloapp Hello-world program |
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22 loadagent Flash manipulation and XRAM loading agent |
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23 lunadrv Driver for Luna LCD (hw exists only at FreeCalypso HQ) |
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24 pirexplore Pirelli DP-L10 hardware exploration program |
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25 simtest Low-level exerciser for the SIM interface hardware |
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26 |
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27 Aside from c139explore which is built as a binary to be loaded via fc-compalram |
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28 (Compal's bootloader protocol), all of the above programs are built as S-record |
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29 images to be loaded via fc-iram. Once loaded via the respective serial code |
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30 download protocol, each of the listed programs runs interactively, listening |
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31 for and executing commands given over the serial port. The specific set of |
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32 available commands is different for each program as relevant to its function, |
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33 but the command framework is common across the target-utils suite. The command |
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34 interface is text-based, such that each program can be driven manually by a |
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35 human operator once fc-iram or fc-compalram has dropped into the tty pass-thru |
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36 mode, but this same text-based command interface can also be driven by other |
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37 programs: fc-loadtool and fc-xram drive loadagent, and fc-buzplay drives |
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38 buzplayer. |
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39 |
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40 Code architecture and execution environment |
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41 =========================================== |
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42 |
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43 Our target-utils suite is built with the GNU toolchain (gcc+binutils), not TI's |
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44 proprietary TMS470 compiler. Because all of target-utils are meant to run out |
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45 of IRAM rather than flash or XRAM, we compile all code in ARM mode (not Thumb), |
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46 and we build without interworking support (no -mthumb-interwork): the ARMv4T |
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47 architecture implemented by the ARM7TDMI core in the Calypso does not support |
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48 penalty-free ARM/Thumb interworking, thus ARM-only code without interworking |
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49 support is the most efficient option for execution out of IRAM. |
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50 |
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51 Selection of UART for communication |
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52 =================================== |
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53 |
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54 All target-utils programs are interactive, listening for text commands given |
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55 over a serial port. But which UART? The Calypso chip has two UARTs, called |
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56 MODEM and IrDA in the chip docs - which of the two should be used for host |
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57 communication? The answer is a trick original to FreeCalypso: most of our |
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58 target-utils programs that are meant to be loaded via fc-iram expect to be |
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59 loaded specifically via the Calypso boot ROM and not in some other way, and |
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60 they look at some of the IRAM variables left behind by the boot ROM code. The |
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61 boot ROM listens on both UARTs for an interrupt-boot sequence, and once it |
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62 receives that sequence on one of the UARTs, it remembers which UART it was and |
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63 uses that same UART for the rest of the serial code download protocol. We read |
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64 that same variable set by the boot ROM, which depends on the boot ROM version. |
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65 To handle different Calypso boot ROM versions, we read the 16-bit word at 0x1FFE |
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66 (the last 16 bits of the boot ROM image) where TI put the boot ROM version |
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67 number, and we support boot ROM versions 0200 (Calypso C05 rev B silicon) and |
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68 0300 (Calypso C035 silicon). Most target-utils programs won't work (will fail |
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69 to select the UART for communication) if the boot ROM is some unsupported |
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70 version or missing altogether, or if the boot ROM is there, but didn't do the |
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71 loading. |
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72 |
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73 The exceptions are as follows: |
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74 |
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75 * c139explore always uses the MODEM UART as appropriate for Mot C139; |
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76 |
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77 * flash-boot-test (a flashable program described later in this article) always |
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78 uses the IrDA UART; |
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79 |
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80 * helloapp is built in 3 versions: helloapp-bootrom.srec, helloapp-irda.srec |
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81 and helloapp-modem.srec. The first version depends on the boot ROM like |
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82 other programs, the other two versions are built as fixed-IrDA or fixed-MODEM. |
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83 |
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84 Other boot ROM and fc-iram dependencies |
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85 ======================================= |
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86 |
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87 There are two other ways in which target-utils programs that are meant to be |
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88 loaded via fc-iram depend on the Calypso boot ROM: |
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89 |
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90 1) The Calypso gets its clock input from the RF section of the GSM device, and |
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91 the RF block can feed either 13 MHz or 26 MHz to the Calypso - some GSM RF |
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92 transceiver chips require 13 MHz (TI Clara), others require 26 MHz (TI Rita |
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93 and Silabs Aero II), yet others can work with either clock (Silabs Aero+), |
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94 and some use a 26 MHz crystal but have the option of feeding either 13 or |
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95 26 MHz to the Calypso (Aero II). The Calypso initially boots without knowing |
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96 what clock frequency it is running at, but then it needs to be told via a |
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97 register setting what the input clock frequency is, so that all peripherals |
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98 (both GSM-specific and general-purpose) always run at 13 MHz. |
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99 |
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100 When the Calypso boot process is interrupted and diverted to serial code |
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101 download in the boot ROM, the boot ROM code autodetects whether the CLKTCXO |
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102 input runs at 13 MHz or 26 MHz (it tries both register bit settings until |
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103 the serial '<' characters sent by the host at 19200 baud are received |
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104 correctly), and if the CLKTCXO input is 26 MHz, the VCLKOUT_DIV2 bit is set |
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105 in the FFFF:FD02 register. Most of our target-utils programs have no hard- |
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106 coded knowledge of the 13 MHz vs. 26 MHz board hardware configuration and |
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107 rely on the Calypso boot ROM to set the division control bits in the |
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108 FFFF:FD02 register correctly for the autodetected clock. |
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109 |
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110 2) The boot ROM allows the serial download host (fc-iram in our case) to |
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111 configure the Calypso DPLL, allowing the ARM7 core to run at its maximum |
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112 frequency of 52 MHz on Calypso C035 or 39 MHz on the older Calypso C05 |
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113 silicon. None of our target-utils programs do their own DPLL setup, instead |
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114 they run with whatever they were booted with - therefore, in order for the |
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115 IRAM programs to run at their intended fastest speed, the correct -h option |
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116 needs to be given to fc-iram, selecting a hardware parameter file with the |
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117 right pll-config setting. |
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118 |
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119 Delay loop timing |
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120 ================= |
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121 |
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122 There are a few places in target-utils where a delay of some specific duration |
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123 needs to be inserted. In most cases the requirement is for a certain minimum |
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124 delay, with more delay time being harmless except for inefficiency, but there |
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125 is one case (SPCA552E chip initialization in pirexplore) where the delay |
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126 requirement is strict: if the delays are too short or too long, the LCD doesn't |
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127 work. In target-utils all of these delays are implemented with CPU-cycle-count |
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128 delay loops that are calibrated at software design time; if the code runs out |
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129 of IRAM and the ARM7 core runs at 52 MHz, the delays will be exactly as |
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130 designed, otherwise they will be longer. In the case of pirexplore the strict |
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131 timing requirement is satisfied by loading and running the program via fc-iram |
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132 -h pirelli, resulting in the correct 52 MHz clock configuration; in all other |
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133 cases running at a frequency below 52 MHz or running out of flash (the |
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134 flash-boot-test special case) produces longer-than-needed delays. |
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135 |
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136 Common interactive commands |
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137 =========================== |
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138 |
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139 The exact set of implemented commands is different for each target-utils |
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140 program, including commands specific to each program's unique function, but the |
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141 following basic commands are included in most programs: |
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142 |
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143 abbinit Initialize ABB communication |
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144 abbpage2 Unlock access to ABB register page 2 |
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145 abbr pg reg Read ABB register <reg> on page <pg> |
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146 abbw pg reg val Write <val> into register <reg> on page <pg> |
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147 dump hex-start hex-len Display a human-oriented memory dump in hex and ASCII |
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148 jump addr Jump to given address with BX |
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149 poweroff Execute Iota ABB soft poweroff (DEVOFF) |
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150 r8 addr Read an 8-bit register or memory location |
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151 r16 addr Read a 16-bit register or memory location |
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152 r32 addr Read a 32-bit register or memory location |
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153 w8 addr data Write an 8-bit register or memory location |
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154 w16 addr data Write a 16-bit register or memory location |
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155 w32 addr data Write a 32-bit register or memory location |
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156 |
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157 For further details, please refer to the source code - if you are playing with |
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158 such low-level components, you need to put on the hat of a developer rather |
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159 than a mere user. |
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160 |
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161 ABB support in target-utils |
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162 =========================== |
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163 |
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164 Our target-utils suite includes code for initializing and executing SPI |
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165 communication with the Iota ABB device (TWL3014 or TWL3025), Calypso's analog |
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166 and power management companion chip. Only Iota ABB type is supported, not |
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167 Omega/Nausica or Syren. The primary reason for having this infrastructure is |
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168 to be able to perform a soft poweroff operation, i.e., to return the Calypso |
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169 phone or modem to its switched-off state after flashing or various standalone |
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170 debug operations, but once implemented, this same ABB SPI communication |
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171 infrastructure is also used in model-specific hardware exploration utilities |
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172 for functions like keypad backlight and vibrator control which are implemented |
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173 via the ABB on some models, and it is used in simtest to control the part of |
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174 the SIM interface that resides in the Iota ABB. |
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175 |
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176 Aside from specialized programs like c139explore that are specific to target |
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177 devices known to use the Iota ABB, most target-utils programs do not execute |
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178 any ABB or SPI communication code (not even initialization) until they receive |
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179 one of the ABB commands: abbinit, abbr, abbw or poweroff. This way if someone |
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180 comes across a Calypso device that has a different ABB type or needs to debug a |
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181 board with broken ABB communication, one can explore other functions without |
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182 touching ABB commands. (simtest is another exception: even though it is not |
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183 specific to one particular target device like c139explore, its main function of |
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184 exercising the SIM interface depends on the Iota ABB, thus it is restricted to |
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185 Calypso+Iota targets.) |
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186 |
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187 The abb_init() function invoked by the abbinit command may be invoked multiple |
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188 times: it maintains an internal flag remembering if the initialization steps |
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189 have already been done or not, and repeated invokations do nothing. User- |
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190 friendly abbr, abbw and poweroff commands invoke abb_init() internally, but the |
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191 special abbpage2 command does not - if you are interested in exploring the |
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192 undocumented register page 2, you need to execute abbinit manually first, then |
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193 abbpage2, then explore with abbr and abbw. |
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194 |
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195 poweroff operation details: VRPCAUX and VRPCDEV |
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196 =============================================== |
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197 |
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198 The abb_power_off() function invoked by the poweroff command performs the |
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199 following sequence of steps: |
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200 |
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201 * Calls abb_init() to establish ABB communication in the case that it hasn't |
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202 already been done; |
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203 |
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204 * Executes the magic writes to TAPCTRL and TAPREG registers that unlock access |
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205 to register page 2 - this step is factored out into the abb_unlock_page2() |
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206 function which is also accessible as the abbpage2 command; |
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207 |
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208 * Writes 0x007 into the undocumented VRPCAUX register to clear the erratic |
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209 state that will be there if we got booted via nTESTRESET rather than PWON; |
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210 |
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211 * Flushes all UART output, i.e., waits for it to finish going out on the wire; |
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212 |
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213 * Writes 0x001 into the VRPCDEV register, which is the actual DEVOFF command. |
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214 |
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215 The step of writing into VRPCAUX and its prerequisite page 2 unlock steps are a |
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216 recent addition as of fc-host-tools-r11; these steps have been added to fix the |
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217 erratic behaviour that was occurring on TI/FC development boards (D-Sample and |
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218 FCDEV3B) when fc-loadtool (or fc-iram with some specialized target-utils |
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219 program) was entered via the RESET button rather than PWON, followed by the |
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220 soft poweroff operation and another switch-on via PWON. For more details, |
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221 please refer to the Calypso-test-reset article in the freecalypso-docs |
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222 repository. |
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223 |
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224 If you are interested in doing some experiments of your own with this |
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225 undocumented quirk of the Calypso+Iota chipset and the odd behaviour it can |
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226 cause, you can do the following: |
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227 |
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228 * To see the content of the undocumented VRPCAUX register resulting from |
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229 different boot modes, execute these commands: |
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230 |
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231 abbinit |
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232 abbpage2 |
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233 abbr 2 30 |
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234 |
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235 Our abbr and abbw commands support page 2, but if you don't issue the magic |
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236 register writes encapsulated in the abbpage2 command, the Iota chip itself |
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237 disallows access to page 2. |
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238 |
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239 * To perform a DEVOFF operation without cleaning up VRPCAUX first (to see the |
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240 resulting erratic behaviour with your own eyes), do it manually as follows: |
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241 |
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242 abbw 0 30 1 |
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243 |
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244 flash-boot-test |
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245 =============== |
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246 |
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247 In addition to the repertoire of run-from-IRAM (loadable via fc-iram) programs |
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248 that form the main course of target-utils, we have a flashable program called |
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249 flash-boot-test - it will be called FBT for short in this article. FBT is a |
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250 test case for the "main application" in flash, and it can be flashed in the |
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251 place of a regular firmware image for certain very low-level tests. Because it |
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252 runs via the flash boot path and does not get loaded serially, FBT is quite |
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253 hardware-specific by necessity: it assumes a platform with 26 MHz Calypso clock |
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254 input and always uses the IrDA UART for communication (hard-coded). FBT was |
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255 written with FCDEV3B and Openmoko GTA02 boards in mind; it won't work on a |
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256 D-Sample board because of the 13 MHz vs. 26 MHz clock difference. |
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257 |
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258 FBT is built in two versions: fbt-mode0.bin and fbt-mode1.bin, differing in the |
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259 magic words at location 0x2000 which tell the Calypso boot ROM how the main |
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260 application in flash should be booted - please refer to the Flash-boot-modes |
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261 article in the freecalypso-docs repository. Only the magic words differ between |
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262 fbt-mode0.bin and fbt-mode1.bin versions; the main body of the code is exactly |
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263 the same. Once it receives control from the boot ROM in whichever mode it was |
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264 booted in, FBT's own code in main.c does the absolute minimum initialization to |
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265 allow serial communication (sets the VCLKOUT_DIV2 bit in the FFFF:FD02 register |
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266 and initializes the IrDA UART) and falls into the same interactive mode of |
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267 operation (listening for text-based commands) as our various run-from-IRAM |
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268 programs, allowing the operator to explore system state as closely out of boot |
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269 as possible. |
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270 |
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271 When a main application in flash is booted in mode 1 (with the boot ROM moved |
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272 out of the way), the Calypso watchdog timer is running, and our FBT program |
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273 does not a perform a watchdog disable step on its own. Therefore, if you flash |
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274 fbt-mode1.bin and boot it, you will see it keep endlessly rebooting about every |
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275 9 s. To stop this endless reboot cycle, issue a wd (watchdog disable) command: |
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276 it is short enough to be easily typed in the available 9 s window. The same |
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277 issue does not occur in flash boot mode 0, as the Calypso boot ROM does disable |
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278 the watchdog and leaves it disabled when booting mode 0 flash images or serially |
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279 downloaded code. |
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280 |
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281 FBT also has a few other commands that have been added to facilitate further |
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282 experimentation with the watchdog timer feature of the Calypso chip - please |
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283 refer to the source code. |