FreeCalypso > hg > freecalypso-tools
annotate target-utils/libbase/serio.S @ 452:688380565e0f
rvinterf/asyncshell/helpfile: unterm addition documented
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 08 Feb 2019 02:14:53 +0000 |
parents | da6df2c626cf |
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1 #include "ns16550.h" |
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2 |
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3 @ this module implements the elementary serial I/O operations |
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4 |
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5 .comm uart_base,4,4 |
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Mychaela Falconia <falcon@freecalypso.org>
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6 |
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7 .text |
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8 .code 32 |
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9 .global serial_out |
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10 serial_out: |
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Mychaela Falconia <falcon@freecalypso.org>
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11 ldr r1, =uart_base |
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12 ldr r2, [r1] |
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target-utils: wait for FIFO not full in serial_out() instead of FIFO empty
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13 1: ldrb r3, [r2, #0x11] @ Calypso UART non-std register SSR |
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Mychaela Falconia <falcon@freecalypso.org>
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14 tst r3, #0x01 @ Tx FIFO full flag |
da6df2c626cf
target-utils: wait for FIFO not full in serial_out() instead of FIFO empty
Mychaela Falconia <falcon@freecalypso.org>
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15 bne 1b |
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16 strb r0, [r2, #NS16550_THR] |
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17 bx lr |
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18 |
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19 .global serial_in_poll |
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parents:
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20 serial_in_poll: |
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parents:
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21 ldr r1, =uart_base |
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parents:
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22 ldr r2, [r1] |
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23 ldrb r3, [r2, #NS16550_LSR] |
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24 tst r3, #NS16550_LSR_DR |
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25 ldrneb r0, [r2, #NS16550_RBR] |
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26 mvneq r0, #0 |
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27 bx lr |
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28 |
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29 .global serial_flush |
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30 serial_flush: |
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31 ldr r1, =uart_base |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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32 ldr r2, [r1] |
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33 1: ldrb r3, [r2, #NS16550_LSR] |
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34 tst r3, #NS16550_LSR_TEMP |
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35 beq 1b |
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36 bx lr |