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fc-loadtool help: improve language regarding 16 MiB flash chips In FC project history, 16 MiB flash originally meant Pirelli DP-L10. Then we got FCDEV3B with the same flash (our own design), but now we are discovering more Calypso devices that used such large flash, both late Calypso era (Sony Ericsson K2x0) as well as much earlier ones (FIC FLUID devices.txt file with 2004 dates, Leonardo+ rev 5). Hence we need to migrate to more generic or neutral language in associated documentation, without giving elevated status to specific examples that drove our early project history.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 03 Dec 2023 21:11:12 +0000
parents ae237e4e8d9b
children
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1 FreeCalypso target-utils suite
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2 ==============================
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3
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4 We have a suite of standalone programs and specialized code pieces that run on
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5 the Calypso ARM7 processor, but are not regular operational phone or modem
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6 firmware; this suite of code bits is called target-utils, maintained and
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7 distributed together with FreeCalypso host tools. The primary reason for the
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8 coupling between FC host tools and target-utils is that the target-utils suite
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9 provides the loadagent target program for fc-loadtool and fc-xram host tools,
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10 as well as compalstage code pieces needed for operating on Compal phones.
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11
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12 Most programs in the target-utils suite are meant to execute out of RAM
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13 (specifically, the Calypso chip's internal RAM or IRAM for short), loaded and
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14 run via fc-iram or fc-compalram - they are not meant to be flashed. As of this
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15 writing, the following run-from-RAM programs are available:
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16
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17 buzplayer Player for buzzer melodies, used by fc-buzplay
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18 c139explore Mot C139 hardware exploration program
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19 calversion Calypso version ID tool, primarily for the DSP ROM version
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20 dspdump Calypso DSP ROM dump tool
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21 helloapp Hello-world program
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22 loadagent Flash manipulation and XRAM loading agent
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72feb9763de4 lunadrv documentation updates for upcoming release
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23 lunadrv Driver for FreeCalypso Luna LCD
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24 pirexplore Pirelli DP-L10 hardware exploration program
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25 simagent SIM interface agent to be used by fc-simint and fc-simtool
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26 simtest Previous low-level exerciser for the SIM interface hardware
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28 Aside from c139explore which is built as a binary to be loaded via fc-compalram
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29 (Compal's bootloader protocol), all of the above programs are built as S-record
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30 images to be loaded via fc-iram. Once loaded via the respective serial code
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31 download protocol, each of the listed programs runs interactively, listening
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32 for and executing commands given over the serial port. The specific set of
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33 available commands is different for each program as relevant to its function,
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34 but the command framework is common across the target-utils suite. The command
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35 interface is text-based, such that each program can be driven manually by a
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36 human operator once fc-iram or fc-compalram has dropped into the tty pass-thru
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37 mode, but this same text-based command interface can also be driven by other
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38 programs: fc-loadtool and fc-xram drive loadagent, and fc-buzplay drives
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39 buzplayer.
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40
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41 Code architecture and execution environment
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42 ===========================================
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43
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44 Our target-utils suite is built with the GNU toolchain (gcc+binutils), not TI's
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45 proprietary TMS470 compiler. Because all of target-utils are meant to run out
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46 of IRAM rather than flash or XRAM, we compile all code in ARM mode (not Thumb),
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47 and we build without interworking support (no -mthumb-interwork): the ARMv4T
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48 architecture implemented by the ARM7TDMI core in the Calypso does not support
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49 penalty-free ARM/Thumb interworking, thus ARM-only code without interworking
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50 support is the most efficient option for execution out of IRAM.
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51
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52 Selection of UART for communication
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53 ===================================
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54
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55 All target-utils programs are interactive, listening for text commands given
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56 over a serial port. But which UART? The Calypso chip has two UARTs, called
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57 MODEM and IrDA in the chip docs - which of the two should be used for host
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58 communication? The answer is a trick original to FreeCalypso: most of our
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59 target-utils programs that are meant to be loaded via fc-iram expect to be
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60 loaded specifically via the Calypso boot ROM and not in some other way, and
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61 they look at some of the IRAM variables left behind by the boot ROM code. The
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62 boot ROM listens on both UARTs for an interrupt-boot sequence, and once it
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63 receives that sequence on one of the UARTs, it remembers which UART it was and
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64 uses that same UART for the rest of the serial code download protocol. We read
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65 that same variable set by the boot ROM, which depends on the boot ROM version.
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66 To handle different Calypso boot ROM versions, we read the 16-bit word at 0x1FFE
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67 (the last 16 bits of the boot ROM image) where TI put the boot ROM version
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68 number, and we support boot ROM versions 0200 (Calypso C05 rev B silicon) and
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69 0300 (Calypso C035 silicon). Most target-utils programs won't work (will fail
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70 to select the UART for communication) if the boot ROM is some unsupported
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71 version or missing altogether, or if the boot ROM is there, but didn't do the
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72 loading.
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73
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74 The exceptions are as follows:
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75
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76 * c139explore always uses the MODEM UART as appropriate for Mot C139;
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77
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78 * flash-boot-test (a flashable program described later in this article) always
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79 uses the IrDA UART;
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80
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81 * helloapp is built in 3 versions: helloapp-bootrom.srec, helloapp-irda.srec
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82 and helloapp-modem.srec. The first version depends on the boot ROM like
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83 other programs, the other two versions are built as fixed-IrDA or fixed-MODEM.
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84
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85 Other boot ROM and fc-iram dependencies
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86 =======================================
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87
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88 There are two other ways in which target-utils programs that are meant to be
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89 loaded via fc-iram depend on the Calypso boot ROM:
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90
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91 1) The Calypso gets its clock input from the RF section of the GSM device, and
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92 the RF block can feed either 13 MHz or 26 MHz to the Calypso - some GSM RF
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93 transceiver chips require 13 MHz (TI Clara), others require 26 MHz (TI Rita
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94 and Silabs Aero II), yet others can work with either clock (Silabs Aero+),
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95 and some use a 26 MHz crystal but have the option of feeding either 13 or
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96 26 MHz to the Calypso (Aero II). The Calypso initially boots without knowing
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97 what clock frequency it is running at, but then it needs to be told via a
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98 register setting what the input clock frequency is, so that all peripherals
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99 (both GSM-specific and general-purpose) always run at 13 MHz.
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100
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101 When the Calypso boot process is interrupted and diverted to serial code
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102 download in the boot ROM, the boot ROM code autodetects whether the CLKTCXO
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103 input runs at 13 MHz or 26 MHz (it tries both register bit settings until
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104 the serial '<' characters sent by the host at 19200 baud are received
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105 correctly), and if the CLKTCXO input is 26 MHz, the VCLKOUT_DIV2 bit is set
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106 in the FFFF:FD02 register. Most of our target-utils programs have no hard-
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107 coded knowledge of the 13 MHz vs. 26 MHz board hardware configuration and
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108 rely on the Calypso boot ROM to set the division control bits in the
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109 FFFF:FD02 register correctly for the autodetected clock.
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110
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111 2) The boot ROM allows the serial download host (fc-iram in our case) to
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112 configure the Calypso DPLL, allowing the ARM7 core to run at its maximum
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113 frequency of 52 MHz on Calypso C035 or 39 MHz on the older Calypso C05
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114 silicon. None of our target-utils programs do their own DPLL setup, instead
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115 they run with whatever they were booted with - therefore, in order for the
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116 IRAM programs to run at their intended fastest speed, the correct -h option
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117 needs to be given to fc-iram, selecting a hardware parameter file with the
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118 right pll-config setting.
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119
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120 Delay loop timing
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121 =================
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122
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123 There are a few places in target-utils where a delay of some specific duration
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124 needs to be inserted. In most cases the requirement is for a certain minimum
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125 delay, with more delay time being harmless except for inefficiency, but there
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126 is one case (SPCA552E chip initialization in pirexplore) where the delay
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127 requirement is strict: if the delays are too short or too long, the LCD doesn't
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128 work. In target-utils all of these delays are implemented with CPU-cycle-count
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129 delay loops that are calibrated at software design time; if the code runs out
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130 of IRAM and the ARM7 core runs at 52 MHz, the delays will be exactly as
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131 designed, otherwise they will be longer. In the case of pirexplore the strict
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132 timing requirement is satisfied by loading and running the program via fc-iram
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133 -h pirelli, resulting in the correct 52 MHz clock configuration; in all other
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134 cases running at a frequency below 52 MHz or running out of flash (the
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135 flash-boot-test special case) produces longer-than-needed delays.
528
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136
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137 Common interactive commands
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138 ===========================
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139
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140 The exact set of implemented commands is different for each target-utils
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141 program, including commands specific to each program's unique function, but the
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142 following basic commands are included in most programs:
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143
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144 abbinit Initialize ABB communication
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145 abbpage2 Unlock access to ABB register page 2
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146 abbr pg reg Read ABB register <reg> on page <pg>
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147 abbw pg reg val Write <val> into register <reg> on page <pg>
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148 dump hex-start hex-len Display a human-oriented memory dump in hex and ASCII
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149 jump addr Jump to given address with BX
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150 poweroff Execute Iota ABB soft poweroff (DEVOFF)
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151 r8 addr Read an 8-bit register or memory location
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152 r16 addr Read a 16-bit register or memory location
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153 r32 addr Read a 32-bit register or memory location
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154 w8 addr data Write an 8-bit register or memory location
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155 w16 addr data Write a 16-bit register or memory location
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156 w32 addr data Write a 32-bit register or memory location
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157
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158 For further details, please refer to the source code - if you are playing with
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159 such low-level components, you need to put on the hat of a developer rather
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160 than a mere user.
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161
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162 ABB support in target-utils
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163 ===========================
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164
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165 Our target-utils suite includes code for initializing and executing SPI
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166 communication with the Iota ABB device (TWL3014 or TWL3025), Calypso's analog
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167 and power management companion chip. Only Iota ABB type is supported, not
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168 Omega/Nausica or Syren. The primary reason for having this infrastructure is
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169 to be able to perform a soft poweroff operation, i.e., to return the Calypso
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170 phone or modem to its switched-off state after flashing or various standalone
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171 debug operations, but once implemented, this same ABB SPI communication
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172 infrastructure is also used in model-specific hardware exploration utilities
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173 for functions like keypad backlight and vibrator control which are implemented
787
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174 via the ABB on some models, and it is used in simagent and simtest to control
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175 the part of the SIM interface that resides in the Iota ABB.
528
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176
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177 Aside from specialized programs like c139explore that are specific to target
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178 devices known to use the Iota ABB, most target-utils programs do not execute
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179 any ABB or SPI communication code (not even initialization) until they receive
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180 one of the ABB commands: abbinit, abbr, abbw or poweroff. This way if someone
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181 comes across a Calypso device that has a different ABB type or needs to debug a
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182 board with broken ABB communication, one can explore other functions without
787
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183 touching ABB commands. (simagent and simtest constitute another exception:
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184 even though these programs aren't specific to one particular target device like
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185 c139explore, their main function of exercising the SIM interface depends on the
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186 Iota ABB, thus they are restricted to Calypso+Iota targets.)
528
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187
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188 The abb_init() function invoked by the abbinit command may be invoked multiple
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189 times: it maintains an internal flag remembering if the initialization steps
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190 have already been done or not, and repeated invokations do nothing. User-
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191 friendly abbr, abbw and poweroff commands invoke abb_init() internally, but the
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192 special abbpage2 command does not - if you are interested in exploring the
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193 undocumented register page 2, you need to execute abbinit manually first, then
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194 abbpage2, then explore with abbr and abbw.
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195
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196 poweroff operation details: VRPCAUX and VRPCDEV
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197 ===============================================
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198
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199 The abb_power_off() function invoked by the poweroff command performs the
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200 following sequence of steps:
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201
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202 * Calls abb_init() to establish ABB communication in the case that it hasn't
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203 already been done;
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204
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205 * Executes the magic writes to TAPCTRL and TAPREG registers that unlock access
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206 to register page 2 - this step is factored out into the abb_unlock_page2()
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diff changeset
207 function which is also accessible as the abbpage2 command;
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208
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209 * Writes 0x007 into the undocumented VRPCAUX register to clear the erratic
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210 state that will be there if we got booted via nTESTRESET rather than PWON;
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211
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212 * Flushes all UART output, i.e., waits for it to finish going out on the wire;
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213
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214 * Writes 0x001 into the VRPCDEV register, which is the actual DEVOFF command.
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215
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diff changeset
216 The step of writing into VRPCAUX and its prerequisite page 2 unlock steps are a
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217 recent addition as of fc-host-tools-r11; these steps have been added to fix the
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diff changeset
218 erratic behaviour that was occurring on TI/FC development boards (D-Sample and
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diff changeset
219 FCDEV3B) when fc-loadtool (or fc-iram with some specialized target-utils
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diff changeset
220 program) was entered via the RESET button rather than PWON, followed by the
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diff changeset
221 soft poweroff operation and another switch-on via PWON. For more details,
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diff changeset
222 please refer to the Calypso-test-reset article in the freecalypso-docs
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diff changeset
223 repository.
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diff changeset
224
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diff changeset
225 If you are interested in doing some experiments of your own with this
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226 undocumented quirk of the Calypso+Iota chipset and the odd behaviour it can
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diff changeset
227 cause, you can do the following:
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228
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229 * To see the content of the undocumented VRPCAUX register resulting from
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diff changeset
230 different boot modes, execute these commands:
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diff changeset
231
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diff changeset
232 abbinit
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233 abbpage2
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234 abbr 2 30
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diff changeset
235
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diff changeset
236 Our abbr and abbw commands support page 2, but if you don't issue the magic
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diff changeset
237 register writes encapsulated in the abbpage2 command, the Iota chip itself
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diff changeset
238 disallows access to page 2.
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diff changeset
239
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240 * To perform a DEVOFF operation without cleaning up VRPCAUX first (to see the
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diff changeset
241 resulting erratic behaviour with your own eyes), do it manually as follows:
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242
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diff changeset
243 abbw 0 30 1
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diff changeset
244
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diff changeset
245 flash-boot-test
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diff changeset
246 ===============
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diff changeset
247
529
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diff changeset
248 In addition to the repertoire of run-from-IRAM (loadable via fc-iram) programs
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
249 that form the main course of target-utils, we have a flashable program called
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
250 flash-boot-test - it will be called FBT for short in this article. FBT is a
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
251 test case for the "main application" in flash, and it can be flashed in the
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
252 place of a regular firmware image for certain very low-level tests. Because it
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
253 runs via the flash boot path and does not get loaded serially, FBT is quite
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
254 hardware-specific by necessity: it assumes a platform with 26 MHz Calypso clock
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
255 input and always uses the IrDA UART for communication (hard-coded). FBT was
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
256 written with FCDEV3B and Openmoko GTA02 boards in mind; it won't work on a
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
257 D-Sample board because of the 13 MHz vs. 26 MHz clock difference.
30bec872824a doc/Target-utils: flash-boot-test documented
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diff changeset
258
30bec872824a doc/Target-utils: flash-boot-test documented
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259 FBT is built in two versions: fbt-mode0.bin and fbt-mode1.bin, differing in the
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260 magic words at location 0x2000 which tell the Calypso boot ROM how the main
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261 application in flash should be booted - please refer to the Flash-boot-modes
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262 article in the freecalypso-docs repository. Only the magic words differ between
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263 fbt-mode0.bin and fbt-mode1.bin versions; the main body of the code is exactly
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264 the same. Once it receives control from the boot ROM in whichever mode it was
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265 booted in, FBT's own code in main.c does the absolute minimum initialization to
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266 allow serial communication (sets the VCLKOUT_DIV2 bit in the FFFF:FD02 register
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267 and initializes the IrDA UART) and falls into the same interactive mode of
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268 operation (listening for text-based commands) as our various run-from-IRAM
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269 programs, allowing the operator to explore system state as closely out of boot
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270 as possible.
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271
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272 When a main application in flash is booted in mode 1 (with the boot ROM moved
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273 out of the way), the Calypso watchdog timer is running, and our FBT program
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274 does not a perform a watchdog disable step on its own. Therefore, if you flash
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275 fbt-mode1.bin and boot it, you will see it keep endlessly rebooting about every
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276 9 s. To stop this endless reboot cycle, issue a wd (watchdog disable) command:
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277 it is short enough to be easily typed in the available 9 s window. The same
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278 issue does not occur in flash boot mode 0, as the Calypso boot ROM does disable
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279 the watchdog and leaves it disabled when booting mode 0 flash images or serially
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280 downloaded code.
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281
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282 FBT also has a few other commands that have been added to facilitate further
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283 experimentation with the watchdog timer feature of the Calypso chip - please
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284 refer to the source code.