FreeCalypso > hg > freecalypso-tools
annotate target-utils/calversion/dsp_bringup.c @ 995:74024eb17e04
fc-loadtool help: improve language regarding 16 MiB flash chips
In FC project history, 16 MiB flash originally meant Pirelli DP-L10.
Then we got FCDEV3B with the same flash (our own design), but now we are
discovering more Calypso devices that used such large flash, both late
Calypso era (Sony Ericsson K2x0) as well as much earlier ones (FIC FLUID
devices.txt file with 2004 dates, Leonardo+ rev 5). Hence we need to
migrate to more generic or neutral language in associated documentation,
without giving elevated status to specific examples that drove our
early project history.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 03 Dec 2023 21:11:12 +0000 |
parents | ca98f800bbf3 |
children |
rev | line source |
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441
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1 /* |
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2 * This module contains the dsp_power_on() function from TCS211, |
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3 * stripped and adapted for the present DSP version determination |
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4 * standalone program. |
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5 */ |
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6 |
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7 #include "types.h" |
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8 #include "leadapi.h" |
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9 #include "dsp_const.h" |
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10 #include "dsp_defty.h" |
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11 |
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12 /* definitions originally in l1_types.h */ |
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13 |
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14 typedef unsigned char BOOL; |
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15 typedef char CHAR; |
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16 |
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17 typedef unsigned char UWORD8; |
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18 typedef signed char WORD8; |
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19 |
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20 typedef unsigned short UWORD16; |
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21 typedef short WORD16; |
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22 |
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23 typedef unsigned long UWORD32; |
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24 typedef long WORD32; |
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25 |
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26 /* definitions originally in l1_confg.h */ |
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27 |
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28 #define DSP_START 0x7000 |
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29 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer |
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30 |
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31 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips |
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32 |
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33 #define C_DSP_SW_WORK_AROUND 0x000E |
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34 |
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35 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. |
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36 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. |
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37 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. |
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38 |
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39 /* DSP reset control register definitions */ |
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40 |
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41 #define MEM_CLKM_ADDR 0xfffffd00 /* CLKM registers addr. */ |
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42 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */ |
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43 |
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44 #define CLKM_LEAD_RST 0x0002 |
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45 #define CLKM_EXT_RST 0x0004 |
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46 |
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47 /*-------------------------------------------------------*/ |
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48 /* dsp_power_on() */ |
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49 /*-------------------------------------------------------*/ |
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50 /* Parameters : */ |
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51 /* Return : */ |
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52 /* Functionality : */ |
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53 /* Remarq : USART Buffer is 256 characters. While USART*/ |
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54 /* is not run during Application_Initialize */ |
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55 /* (hisrs not served because Nucleus scheduler*/ |
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56 /* is not running yet) : */ |
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57 /* ==> check string size < 256 !!!!!! */ |
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58 /*-------------------------------------------------------*/ |
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59 void dsp_power_on(void) |
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60 { |
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61 UWORD16 dsp_start_address; |
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62 UWORD16 param_size; |
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63 |
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64 API i; |
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65 volatile API *pt; |
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66 WORD16 j; |
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67 |
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68 volatile T_NDB_MCU_DSP * dsp_ndb_ptr; |
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69 |
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70 static API_SIGNED param_tab[] = { |
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71 |
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72 D_TRANSFER_RATE, |
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73 |
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74 // ..................Latencies |
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75 D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM, |
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76 |
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77 D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM, |
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78 |
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79 //...................p_gprs_install_adress |
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80 D_HOLE, |
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81 |
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82 //...................d_misc_config |
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83 D_MISC_CONFIG, |
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84 |
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85 //...................d_cn_sw_workaround |
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86 C_DSP_SW_WORK_AROUND, |
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87 |
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88 //...................Reserved |
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89 D_HOLE, D_HOLE, |
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90 D_HOLE, D_HOLE, |
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91 |
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92 //...................Frequency burst |
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93 D_FB_MARGIN_BEG, D_FB_MARGIN_END, |
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94 D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, |
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95 D_FB_THR_DET_TRACK, |
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96 //...................Demodulation |
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97 D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, |
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98 D_DEM_POND_RED, |
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99 //...................TCH Full Speech |
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100 D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, |
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101 D_GU, D_GO, D_ATTMAX, |
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102 D_SM, D_B, |
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103 |
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104 //...................V42 bis |
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105 D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX, |
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106 D_V42B_RESET_DELAY, |
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107 |
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108 //...................TCH Half Speech |
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109 D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, |
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110 D_GU_HR, D_GO_HR, D_B_HR, |
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111 D_SM_HR, D_ATTMAX_HR, |
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112 |
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113 //...................Added variables for EFR |
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114 C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, |
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115 C_GU_EFR, C_GO_EFR, C_B_EFR, |
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116 C_SM_EFR, C_ATTMAX_EFR, |
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117 |
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118 //...................Full rate variables |
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119 D_SD_MIN_THR_TCHFS, |
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120 D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, |
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121 |
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122 //...................TCH Half Speech |
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123 D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, |
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124 D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, |
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125 |
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126 //...................TCH Enhanced Full Rate Speech |
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127 D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, |
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128 D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI, |
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129 |
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130 D_WED_FIL_TC, D_X_MIN, D_X_MAX, |
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131 D_SLOPE, D_Y_MIN, D_Y_MAX, |
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132 D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, |
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133 |
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134 D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, |
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135 D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT |
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136 }; |
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137 param_size = 79; |
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138 |
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139 // NDB pointer. |
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140 dsp_ndb_ptr = (volatile T_NDB_MCU_DSP *) NDB_ADR; |
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141 |
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142 //------------- |
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143 // DSP STARTUP |
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144 //------------- |
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145 { |
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146 // Release Lead reset before DSP code/patch download to insure proper reset of DSP |
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147 printf("Releasing DSP core from reset\n"); |
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148 (*(unsigned short *) CLKM_CNTL_RST) &= ~CLKM_LEAD_RST; |
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149 |
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150 // GSM 1.5 |
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151 //----------------------------------------------------------------- |
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152 // After RESET release, DSP is in SAM Mode ! while API_CNTR (0xF900) |
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153 // register is in reset state: HOM mode, PLL off, Bridge off. No ws |
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154 // are applied for MCU<-->API access !!!!! So, MCU must wait for |
1dcc9e4b71fd
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155 // end of Leadboot execution before accessing API. |
498
ca98f800bbf3
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441
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156 /* |
ca98f800bbf3
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441
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157 * TI's firmware code waits 10 us, but we'll give it a more generous |
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441
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158 * 1 ms because our clocking setup is a little different, coming from |
ca98f800bbf3
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Mychaela Falconia <falcon@freecalypso.org>
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441
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159 * the boot ROM: on platforms with 13 MHz CLKTCXO the DSP will run |
ca98f800bbf3
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441
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160 * at the same frequency as the ARM, rather than the typical double. |
ca98f800bbf3
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Mychaela Falconia <falcon@freecalypso.org>
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441
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|
161 */ |
ca98f800bbf3
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441
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|
162 wait_ARM_cycles(13000); |
441
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|
163 |
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|
164 // NO DOWNLOAD... |
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165 { |
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|
166 // Wait for READY status from DSP. |
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167 printf("Waiting for DSP bootloader READY status\n"); |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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168 while(*((volatile UWORD16 *)DOWNLOAD_STATUS) != LEAD_READY); |
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|
169 |
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170 // Set DSP start address. |
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171 dsp_start_address = DSP_START; |
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|
172 } |
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|
173 } |
1dcc9e4b71fd
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|
174 |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
175 //-------------------------------------------------------------- |
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176 // Loading of NDB parameters....... |
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177 //-------------------------------------------------------------- |
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178 printf("Loading NDB parameters\n"); |
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179 // Initialize background control variable to No background. Background tasks can be launch in GPRS |
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180 // as in GSM. |
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Mychaela Falconia <falcon@freecalypso.org>
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|
181 dsp_ndb_ptr->d_background_enable = 0; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
182 dsp_ndb_ptr->d_background_abort = 0; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
183 dsp_ndb_ptr->d_background_state = 0; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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184 dsp_ndb_ptr->d_debug_ptr = 0x0074; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
185 dsp_ndb_ptr->d_debug_bk = 0x0001; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
186 dsp_ndb_ptr->d_pll_config = C_PLL_CONFIG; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
187 dsp_ndb_ptr->p_debug_buffer = C_DEBUG_BUFFER_ADD; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
188 dsp_ndb_ptr->d_debug_buffer_size = C_DEBUG_BUFFER_SIZE; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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189 dsp_ndb_ptr->d_debug_trace_type = C_DEBUG_TRACE_TYPE; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
190 |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
191 // Deep Sleep work around used on Calypso |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
192 // This init is used to backward compatibility with old patch. |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
193 dsp_ndb_ptr->d_dsp_state = C_DSP_IDLE3; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
194 |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
195 dsp_ndb_ptr->d_audio_gain_ul = 0; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
196 dsp_ndb_ptr->d_audio_gain_dl = 0; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
197 |
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|
198 // for patch >= 2100, use new AEC |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
199 dsp_ndb_ptr->d_es_level_api = 0x5213; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
200 dsp_ndb_ptr->d_mu_api = 0x5000; |
1dcc9e4b71fd
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|
201 |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
202 //-------------------------------------------------------------- |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
203 // Loading of PARAM area....... |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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|
204 //-------------------------------------------------------------- |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
205 printf("Loading PARAM area\n"); |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
206 // Load PARAM memory... |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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diff
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|
207 pt = (volatile API *) PARAM_ADR; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
208 |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
209 for (i=0; i<param_size; i++) *pt++ = param_tab[i]; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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|
210 |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
211 { |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
212 T_PARAM_MCU_DSP *pt_param = (T_PARAM_MCU_DSP *) PARAM_ADR; |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
213 |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
214 // "d_gprs_install_address" has to be set only if no PATCH is download, i.e. |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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|
215 // "d_gprs_install_address" is automatically set by DSP if a PATCH is download |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
216 pt_param->d_gprs_install_address = INSTALL_ADD; |
1dcc9e4b71fd
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
217 } |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
218 |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
219 printf("Booting DSP main code\n"); |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
220 *(volatile UWORD16 *) DOWNLOAD_SIZE = 0; // Size=0 to force DSP to start from address... |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
221 *(volatile UWORD16 *) DOWNLOAD_ADDR = dsp_start_address; // Start address. |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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222 *(volatile UWORD16 *) DOWNLOAD_STATUS = BLOCK_READY; // Start DSP... |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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223 |
498
ca98f800bbf3
calversion utility: removed osmo_delay_ms()
Mychaela Falconia <falcon@freecalypso.org>
parents:
441
diff
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224 /* give it a very generous 50 ms wait */ |
ca98f800bbf3
calversion utility: removed osmo_delay_ms()
Mychaela Falconia <falcon@freecalypso.org>
parents:
441
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225 wait_ARM_cycles(13000 * 50); |
441
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target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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226 printf("DSP reports version 0x%04X 0x%04X\n", |
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target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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227 dsp_ndb_ptr->d_version_number1, dsp_ndb_ptr->d_version_number2); |
1dcc9e4b71fd
target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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228 } |