FreeCalypso > hg > freecalypso-tools

annotate target-utils/calversion/dsp_const.h @ 995:74024eb17e04

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fc-loadtool help: improve language regarding 16 MiB flash chips In FC project history, 16 MiB flash originally meant Pirelli DP-L10. Then we got FCDEV3B with the same flash (our own design), but now we are discovering more Calypso devices that used such large flash, both late Calypso era (Sony Ericsson K2x0) as well as much earlier ones (FIC FLUID devices.txt file with 2004 dates, Leonardo+ rev 5). Hence we need to migrate to more generic or neutral language in associated documentation, without giving elevated status to specific examples that drove our early project history.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 03 Dec 2023 21:11:12 +0000
parents 1dcc9e4b71fd
children
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441
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1 /*
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2 * This header file is a subset of l1_const.h from TCS211, defining
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3 * those constants which are needed for the DSP bring-up code in
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4 * the dsp_bringup.c module.
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5 */
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6
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7 #define NO_PAR 0
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8
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9 #define NO_TASK 0
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10 #define ALL_TASK 0xffffffff
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11 #define ALL_PARAM 0xffffffff
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12
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13 #define TRUE 1
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14 #define TRUE_L 1L
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15 #define FALSE 0
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16
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17 #define NOT_PENDING 0
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18 #define PENDING 1
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19
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20 #define INACTIVE 2
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21 #define ACTIVE 3
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22 #define RE_ENTERED 4
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23 #define WAIT_IQ 5
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24
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25 //---------------------------------------------
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26 // MCU-DSP bit-field bit position definitions
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27 //---------------------------------------------
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28 #define GPRS_SCHEDULER 1 // Select GPRS scheduler
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29 #define GSM_SCHEDULER 2 // Select GSM scheduler
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30
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31 // DSP state need to be used to enter Deep Sleep mode
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32 #define C_DSP_IDLE3 3
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33
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34 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800)))
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35
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36 // ****************************************************************
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37 // PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
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38 // ****************************************************************
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39 #define C_POND_RED 1L
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40 #define D_NSUBB_IDLE 296L
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41 #define D_NSUBB_DEDIC 30L
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42 #define D_FB_THR_DET_IACQ 0x3333L
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43 #define D_FB_THR_DET_TRACK 0x28f6L
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44 #define D_DC_OFF_THRES 0x7fffL
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45 #define D_DUMMY_THRES 17408L
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46 #define D_DEM_POND_GEWL 26624L
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47 #define D_DEM_POND_RED 20152L
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48 #define D_HOLE 0L
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49 #define D_TRANSFER_RATE 0x6666L
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50
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51 // Full Rate vocoder definitions.
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52 #define D_MACCTHRESH1 7872L
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53 #define D_MLDT -4L
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54 #define D_MACCTHRESH 7872L
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55 #define D_GU 5772L
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56 #define D_GO 7872L
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57 #define D_ATTMAX 53L
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58 #define D_SM -892L
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59 #define D_B 208L
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60 #define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
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61 #define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
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62 #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
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63 #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
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64
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65 // Frequency burst definitions
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66 #define D_FB_MARGIN_BEG 24
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67 #define D_FB_MARGIN_END 22
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68
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69 // V42bis definitions
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70 #define D_V42B_SWITCH_HYST 16L
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71 #define D_V42B_SWITCH_MIN 64L
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72 #define D_V42B_SWITCH_MAX 250L
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73 #define D_V42B_RESET_DELAY 10L
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74
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75 #define D_LAT_MCU_BRIDGE 0x000FL
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76
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77 #define D_LAT_MCU_HOM2SAM 0x000CL
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78
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79 #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
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80 #define D_LAT_DSP_AFTER_SAM 0x0004L
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81
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82 // Background Task in GSM mode: Initialization.
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83 #define D_GSM_BGD_MGT 0L
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84
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85 #define D_MISC_CONFIG 1L
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86
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87 // Half Rate vocoder and ched definitions.
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88
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89 #define D_SD_MIN_THR_TCHHS 37L
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90 #define D_MA_MIN_THR_TCHHS 344L
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91 #define D_MD_MAX_THR_TCHHS 2175L
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92 #define D_MD1_MAX_THR_TCHHS 138L
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93 #define D_SD_AV_THR_TCHHS 1845L
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94 #define D_WED_FIL_TC 0x7c00L
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95 #define D_WED_FIL_INI 4650L
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96 #define D_X_MIN 15L
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97 #define D_X_MAX 23L
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98 #define D_Y_MIN 703L
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99 #define D_Y_MAX 2460L
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100 #define D_SLOPE 135L
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101 #define D_WED_DIFF_THRESHOLD 406L
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102 #define D_MABFI_MIN_THR_TCHHS 5320L
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103 #define D_LDT_HR -5
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104 #define D_MACCTRESH_HR 6500
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105 #define D_MACCTRESH1_HR 6500
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106 #define D_GU_HR 2620
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107 #define D_GO_HR 3700
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108 #define D_B_HR 182
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109 #define D_SM_HR -1608
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110 #define D_ATTMAX_HR 53
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111
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112 // Enhanced Full Rate vocoder and ched definitions.
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113
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114 #define C_MLDT_EFR -4
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115 #define C_MACCTHRESH_EFR 8000
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116 #define C_MACCTHRESH1_EFR 8000
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117 #define C_GU_EFR 4522
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118 #define C_GO_EFR 6500
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119 #define C_B_EFR 174
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120 #define C_SM_EFR -878
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121 #define C_ATTMAX_EFR 53
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122 #define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
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123 #define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
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124 #define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
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125 #define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
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Mychaela Falconia <falcon@freecalypso.org>
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126
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Mychaela Falconia <falcon@freecalypso.org>
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127 // Integrated Data Services definitions.
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Mychaela Falconia <falcon@freecalypso.org>
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128 #define D_MAX_OVSPD_UL 8
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Mychaela Falconia <falcon@freecalypso.org>
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129 // Detect frames containing 90% of 1s as synchro frames
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Mychaela Falconia <falcon@freecalypso.org>
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130 #define D_SYNC_THRES 0x3f50
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Mychaela Falconia <falcon@freecalypso.org>
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131 // IDLE frames are only frames with 100 % of 1s
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Mychaela Falconia <falcon@freecalypso.org>
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132 #define D_IDLE_THRES 0x4000
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Mychaela Falconia <falcon@freecalypso.org>
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133 #define D_M1_THRES 5
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Mychaela Falconia <falcon@freecalypso.org>
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134 #define D_MAX_OVSP_DL 8
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Mychaela Falconia <falcon@freecalypso.org>
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135
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Mychaela Falconia <falcon@freecalypso.org>
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136 #define D_FACCH_THR 0
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Mychaela Falconia <falcon@freecalypso.org>
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137 #define D_DSP_TEST 0
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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138 #define D_VERSION_NUMBER 0
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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139 #define D_TI_VERSION 0
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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140
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Mychaela Falconia <falcon@freecalypso.org>
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141 // DSP ADRESSES
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Mychaela Falconia <falcon@freecalypso.org>
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142 //--------------------
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Mychaela Falconia <falcon@freecalypso.org>
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143
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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144 #define DB_SIZE (4*20L) // 4 pages of 20 words...
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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145
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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146 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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147 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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148 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
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Mychaela Falconia <falcon@freecalypso.org>
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149 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
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Mychaela Falconia <falcon@freecalypso.org>
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150 #define NDB_ADR 0xFFD001A8L // NDB start address : 268 words
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Mychaela Falconia <falcon@freecalypso.org>
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151 #define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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152
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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153 #define DB2_R_PAGE_0 0xFFD00184L
1dcc9e4b71fd target-utils/calversion: program written, compiles
Mychaela Falconia <falcon@freecalypso.org>
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154 #define DB2_R_PAGE_1 0xFFD00188L