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srec-regions: removed unnecessary prohibition against address going backward
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 27 Feb 2020 08:12:11 +0000
parents a97d96e0fc5c
children 7b4c011fa798
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a97d96e0fc5c doc: new Loadtool-targets article
Mychaela Falconia <falcon@freecalypso.org>
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1 Explanation of -h targets for fc-loadtool and friends
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2 =====================================================
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3
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4 It is possible to run fc-loadtool without giving it any -h option at all - if
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5 run in this manner, the tool will still gain access to the target Calypso device
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6 via its boot ROM and allow some peeking and poking to be done, but it will run
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7 with some major limitations:
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8
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9 * No PLL multiplier will be set up, thus the Calypso ARM7 core will run at
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10 13 MHz rather than the preferred faster frequency of 39 MHz for Calypso C05
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11 or 52 MHz for Calypso C035.
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12
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13 * In the absence of a hardware parameter file specifying flash configuration,
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14 all high-level flash operations (all commands beginning with flash) will be
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15 disabled. One can still dump the flash manually using the low-level dump2bin
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16 command (as opposed to flash dump2bin), but no other flash manipulations are
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17 possible.
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18
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19 * With most -h hardware parameter files the default exit mode is set to
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20 exit iota-off, but without a hardware parameter file it will be exit bare
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21 by default.
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22
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23 fc-xram is not useful at all without -h: one cannot load anything into XRAM
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24 until Calypso MEMIF is set up properly for XRAM access, and this setup is done
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25 by the init scripts referenced from hardware parameter files.
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26
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27 Available -h targets
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28 ====================
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29
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30 -h compal and -h c155
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31
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32 -h compal needs to be used for all of "lower" Compal subfamilies
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33 (everything other than Mot C155/156); -h c155 is self-explanatory.
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34 Very special loadtools configuration is needed for Compal targets,
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35 telling our tools to use a very different way of gaining entry through
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36 Compal's bootloader and configuring the special flash erase-program-boot
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37 hack.
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38
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39 All following configurations are for more sane, meaning non-Compal targets:
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40
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41 -h c05 and -h c035
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42
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43 These are the most generic configurations we have, indicating only the
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44 use of Calypso C05 or C035, respectively, but no other knowledge about
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45 target hardware. These minimal configs are not usable for flash
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46 manipulation or for fc-xram, but they may be useful for fc-iram or
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47 low-level (non-flash) fc-loadtool operations.
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48
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49 -h c05i and -h c035i
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50
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51 These two configurations are the next step up in target-specific
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52 knowledge from the more basic c05 and c035: the present c05i and c035i
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53 configs additionally indicate the use of a Iota ABB, telling our tools
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54 to perform a Iota poweroff when we are done. They are still not usable
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55 for flash manipulation or for fc-xram, but they are ideal for the
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56 simpler and more specialized fc-buzplay and fc-dspromdump tools.
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57
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58 -h gen4 and -h gen8
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59
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60 These two configs are our most generic fc-loadtool targets: they are
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61 supersets of c035i (Calypso C035 and Iota ABB required), supporting
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62 4 MiB or 8 MiB flash on Calypso nCS0, respectively. More precisely,
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63 our gen4 config supports *up to* 4 MiB of flash, whereas gen8 supports
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64 up to 8 MiB. In the vast majority of cases it is safe and thus easier
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65 to use gen8; the more conservative gen4 config is only needed when you
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66 DON'T want Calypso multifunction pin CS4/ADD22 to be switched from CS4
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67 to ADD22, either because you know for certain that the flash chip is
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68 4 MiB or less or because you found a super-exotic board on which this
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69 pin is actually used as CS4 - we have never seen one of the latter.
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70
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71 These gen4 and gen8 configs set up Calypso MEMIF registers for nCS0 and
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72 nCS1; the latter is assumed to be connected to XRAM and is set up for
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73 fc-xram. MEMIF configuration registers are set up with WS=4 - please
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74 refer to the MEMIF-wait-states article in the freecalypso-docs
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75 repository.
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76
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77 -h dsample
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78
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79 The dsample target is special in two ways:
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80
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81 * The PLL multiplier is set to 3 rather than 4, resulting in 39 MHz
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82 ARM7 core clock instead of 52 MHz - this slowdown is needed because
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83 early D-Sample boards have Calypso C05 chips on them.
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84
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85 * Calypso MEMIF setup is done for nCS0 (flash), nCS1 (main XRAM) and
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86 nCS2 (extra XRAM), making all of D-Sample XRAM available to fc-xram.
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87
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88 For flash manipulation purposes this dsample target is no different
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89 from gen8.
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90
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91 -h fcfam
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92
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93 The only special features of this configuration are:
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94
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95 * Calypso MEMIF setup is done for nCS0, nCS1 and nCS2 like on D-Sample;
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96
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97 * Flash support is configured to look for the second 8 MiB flash bank
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98 on Calypso nCS2.
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99
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100 This configuration is required for flash manipulation on boards like
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101 our current FCDEV3B that have S71PL129N or S71PL129J flash chips with
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102 the second flash chip select wired to Calypso nCS2. This config can be
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103 considered a special superset of gen8: every target that works with
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104 -h gen8 will also work with -h fcfam, but not the other way around.
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105
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106 -h fic
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107
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108 FIC's board wiring that has made its way into Openmoko GTA01 and GTA02
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109 PCBs and was also undoubtedly used on FIC's earlier pre-Openmoko phones
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110 or modems allows for up to 16 MiB of flash (4 MiB, 8 MiB or 16 MiB
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111 flash chips can be populated on the same PCB footprint) with the second
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112 flash chip select wired to Calypso nCS4.
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113
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114 This -h fic config supports all FIC Calypso devices with 4 MiB, 8 MiB
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115 or 16 MiB flash, and like -h fcfam it can be considered a special
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116 superset of gen4 and gen8, special for FIC's board wiring where the
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117 potential 2nd flash chip select goes to nCS4.
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118
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119 -h gta02
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120
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121 This narrowly specialized config is deprecated and will be removed in a
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122 future release of FC host tools; please use the new generalized -h fic
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123 config instead.
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124
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125 -h leonardo
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126
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127 This config is a Calypso C05 counterpart to -h fcfam, i.e., -h leonardo
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128 differs from -h fcfam only in that the Calypso boot ROM is told to
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129 program the PLL with a lower multiplier, running the PLL at 78 MHz
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130 instead of 104 MHz, with the ARM7 core getting 39 MHz instead of 52 MHz.
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131 This slowdown is needed because early Leonardo boards had Calypso C05
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132 chips on them.
a97d96e0fc5c doc: new Loadtool-targets article
Mychaela Falconia <falcon@freecalypso.org>
parents:
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133
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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134 -h pirelli
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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135
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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136 The Pirelli DP-L10 phone has had its own dedicated -h pirelli target
a97d96e0fc5c doc: new Loadtool-targets article
Mychaela Falconia <falcon@freecalypso.org>
parents:
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137 config since the beginning of FreeCalypso, and this special config is
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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138 still needed because these phones have 16 MiB flash chips (either
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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139 S71PL129J or S71PL129N) with the second flash chip select wired to
a97d96e0fc5c doc: new Loadtool-targets article
Mychaela Falconia <falcon@freecalypso.org>
parents:
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140 Calypso nCS3, a wiring arrangement original to this Pirelli DP-L10.
a97d96e0fc5c doc: new Loadtool-targets article
Mychaela Falconia <falcon@freecalypso.org>
parents:
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141
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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142 -h w220
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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143
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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144 Motorola W220 (made by Chi-Mei, *not* a Compal target!) gets its own
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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145 special loadtools config because of its XRAM wiring: the XRAM bank sits
a97d96e0fc5c doc: new Loadtool-targets article
Mychaela Falconia <falcon@freecalypso.org>
parents:
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146 on Calypso nCS3 instead of the usual nCS1.