FreeCalypso > hg > freecalypso-tools

annotate target-utils/simtest/setup.c @ 695:8d7dcfd9df53

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
loadtools: missing #include <unistd.h> in tpinterf modules
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 11 Mar 2020 18:21:22 +0000
parents 06ad5e30e8d0
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
457
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
1 #include "types.h"
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
2 #include "abbdefs.h"
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
3 #include "simregs.h"
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4
495
06ad5e30e8d0 target-utils: wait_ARM_cycles() changed to 4 cycles per loop
Mychaela Falconia <falcon@freecalypso.org>
parents: 457
diff changeset
5 #define WAIT_ONE_TDMA 60000
457
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
6
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7 extern u16 abb_reg_read();
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 extern void abb_reg_write();
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
9
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10 u16 conf1_reg;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 void
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
13 cmd_setup(argbulk)
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14 char *argbulk;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 {
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 u16 abb_sim_reg;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
18 abb_sim_reg = abb_reg_read(VRPCSIM);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
19 if (!(abb_sim_reg & 2)) {
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
20 printf("ERROR: VRSIM is not enabled\n");
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 return;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
22 }
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
23 if (!(abb_sim_reg & 4)) {
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
24 printf("ERROR: VRSIM is not in proper regulation\n");
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
25 return;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
26 }
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
27
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
28 /* TI's SIM_ManualStart() code follows */
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
29 SIMREGS.conf1 = conf1_reg = 0x8004;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
30 SIMREGS.cmd = SIM_CMD_CLKEN;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
31
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
32 SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_STOP;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
33 wait_ARM_cycles(WAIT_ONE_TDMA * 4);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
34
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
35 SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_SWRST;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
36 wait_ARM_cycles(WAIT_ONE_TDMA);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
37
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
38 SIMREGS.conf2 = 0x0940;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
39
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
40 //enter in manual mode to start the ATR sequence
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
41 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_BYPASS;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
42 wait_ARM_cycles(WAIT_ONE_TDMA);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
43
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
44 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SVCCLEV;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
45 wait_ARM_cycles(WAIT_ONE_TDMA);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
46
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
47 abb_sim_reg |= 8;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
48 abb_reg_write(VRPCSIM, abb_sim_reg);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
49 wait_ARM_cycles(WAIT_ONE_TDMA);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
50
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
51 SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_SIOLOW;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
52 wait_ARM_cycles(WAIT_ONE_TDMA);
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
53
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
54 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SCLKEN;
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
55 SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_TXRX; //set to receive mode
d96ea6ae6aa5 simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
56 }