FreeCalypso > hg > freecalypso-tools
annotate loadtools/scripts/dsample.config @ 783:c136a1a2474b
simagent: initial implementation of APDU exchange
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sat, 13 Mar 2021 22:06:08 +0000 |
parents | 49ee210fc4fb |
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rev | line source |
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e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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1 # The following parameters go into the <p command sent to the boot ROM |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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2 # The values to be used have been gleaned from the 20020917 fw image |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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3 |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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4 # CLKTCXO input is 13 MHz on the D-Sample, and with Calypso C05 |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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5 # the max allowed PLL'ed clock is 78 MHz for the DSP and 39 MHz for the ARM. |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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6 # TI's firmware sets the PLL up to multiply by 6 (giving 78 MHz) with |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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7 # divide by 2 for the ARM, but the boot ROM doesn't do the latter when |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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8 # the input clock is 13 MHz. Hence we'll program the PLL to multiply |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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9 # by 3, putting everything at 39 MHz. |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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10 |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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11 pll-config 3/1 |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 rhea-cntl 0x00 # set by 20020917 fw, hence presumed correct |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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14 # The remaining settings are carried out via loadagent commands |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
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15 init-script cs2-4ws-8mb.init |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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16 |
509
49ee210fc4fb
loadtools/scripts/*.config: new flash config
Mychaela Falconia <falcon@freecalypso.org>
parents:
326
diff
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17 # 8 MiB flash, accessible at 0x03000000 without any problems |
49ee210fc4fb
loadtools/scripts/*.config: new flash config
Mychaela Falconia <falcon@freecalypso.org>
parents:
326
diff
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18 flash single-8M 0x03000000 |
0
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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19 |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
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20 # Perform a Iota poweroff when we are done |
e7502631a0f9
initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 exit-mode iota-off |