FreeCalypso > hg > freecalypso-tools

annotate loadtools/scripts/dsample.config @ 390:c7599298998c

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README: updated for the new set of top-level source directories
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 11 Mar 2018 17:39:53 +0000
parents 2b5ed962c2f9
children 49ee210fc4fb
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e7502631a0f9 initial import from freecalypso-sw rev 1033:5ab737ac3ad7
Mychaela Falconia <falcon@freecalypso.org>
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1 # The following parameters go into the <p command sent to the boot ROM
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2 # The values to be used have been gleaned from the 20020917 fw image
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4 # CLKTCXO input is 13 MHz on the D-Sample, and with Calypso C05
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5 # the max allowed PLL'ed clock is 78 MHz for the DSP and 39 MHz for the ARM.
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6 # TI's firmware sets the PLL up to multiply by 6 (giving 78 MHz) with
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7 # divide by 2 for the ARM, but the boot ROM doesn't do the latter when
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8 # the input clock is 13 MHz. Hence we'll program the PLL to multiply
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9 # by 3, putting everything at 39 MHz.
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11 pll-config 3/1
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12 rhea-cntl 0x00 # set by 20020917 fw, hence presumed correct
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14 # The remaining settings are carried out via loadagent commands
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15 init-script cs2-4ws-8mb.init
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17 # 8 MiB flash, accessible at 0x03000000 without Compal-like problems,
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2b5ed962c2f9 loadtools/scripts/dsample.config: use the new 28f640w30b chip type
Mychaela Falconia <falcon@freecalypso.org>
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18 # but the 28F640W30B flash chip has partition quirks, so we need to
2b5ed962c2f9 loadtools/scripts/dsample.config: use the new 28f640w30b chip type
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19 # tell fc-loadtool about it explicitly instead of using CFI.
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20 flash 28f640w30b 0x03000000
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22 # Perform a Iota poweroff when we are done
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23 exit-mode iota-off