annotate target-utils/include/romvars.h @ 1014:961efadd530a default tip

fc-shell TCH DL handler: add support for CSD modes TCH DL capture mechanism in FC Tourmaline firmware has been extended to support CSD modes in addition to speech - add the necessary support on the host tools side. It needs to be noted that this mechanism in its present state does NOT provide the debug utility value that was sought: as we learned only after the code was implemented, TI's DSP has a misfeature in that the buffer we are reading (a_dd_0[]) is zeroed out when the IDS block is enabled, i.e., we are reading all zeros and not the real DL bits we were after. But since the code has already been written, we are keeping it - perhaps we can do some tests with IDS disabled.
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 26 Nov 2024 06:27:43 +0000
parents e7502631a0f9
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1 /*
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2 * Our loadagent will always be loaded into Calypso targets by the on-chip
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3 * boot ROM operating in the UART download mode. The lowest IRAM address
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4 * at which we can load our code is 0x800750; somewhat lower at 0x800518
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5 * the boot ROM downloader has a few variables which may have been intended
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6 * to be private to the boot ROM, but which are useful to us. For example,
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7 * by looking at these variables, we can see which of the two UARTs was
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8 * used to feed our code to the boot ROM, and use the same UART for
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9 * subsequent communication - without building multiple versions of our
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10 * loadagent or resorting to other ugliness.
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11 *
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12 * This header file defines the layout of the IRAM structure in question,
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13 * based on the disassembly of the boot ROM.
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14 */
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16 #ifndef __ROMVARS_H
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17 #define __ROMVARS_H
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19 #include "types.h"
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20
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21 struct boot_rom_vars {
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22 u8 baud_rate_code;
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23 u8 pad1[3];
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24 u32 uart_timeout;
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25 u8 uart_id;
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26 u8 pll_config;
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27 u16 cs_ws_config;
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28 u8 clktcxo_13mhz;
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29 u8 rhea_cntl;
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30 u16 chksum_cmd;
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31 u16 chksum_accum;
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32 u16 pad2;
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33 u32 branch_addr;
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34 };
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36 #endif /* include guard */