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annotate target-utils/include/timer.h @ 302:e05563f0dfcf

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doc/Compal-calibration: Rx calchan ranges documented
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 19 Nov 2017 23:10:07 +0000
parents 0f11da299b7d
children
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1 /*
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2 * Definitions for Calypso general-purpose timer registers
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3 *
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4 * This header is usable from both .c and .S source files.
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5 */
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6
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7 #ifndef _CALYPSO_TIMER_H
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8 #define _CALYPSO_TIMER_H
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9
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10 #define TIMER1_BASE_ADDR 0xFFFE3800
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11 #define TIMER2_BASE_ADDR 0xFFFE6800
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12
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13 #ifdef __ASSEMBLER__
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14
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15 /*
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16 * Assembly source with cpp
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17 *
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18 * The most convenient way to access registers like these from ARM
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19 * assembly is to load the base address of the register block in some
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20 * ARM register, using only one ldr rN, =xxx instruction and only one
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21 * literal pool entry, and then access various registers in the block
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22 * from the same base using the immediate offset addressing mode.
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23 *
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24 * Here we define the offsets for the usage scenario above.
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25 */
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26
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27 #define CNTL_TIM 0x00
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28 #define LOAD_TIM 0x02
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29 #define READ_TIM 0x04
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30
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31 #else
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32
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33 /*
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34 * C source
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35 *
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36 * For access from C, we define the layout of each timer register block
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37 * as a struct, and then define a pleudo-global-var for easy "volatile"
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38 * access to each of the 2 timers.
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39 */
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40
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41 struct timer_regs {
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42 unsigned char cntl;
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43 unsigned char pad;
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44 unsigned short load;
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45 unsigned short read;
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46 };
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47
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48 #define TIMER1_REGS (*(volatile struct timer_regs *) TIMER1_BASE_ADDR)
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49 #define TIMER2_REGS (*(volatile struct timer_regs *) TIMER2_BASE_ADDR)
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50
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51 #endif
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52
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53 /* CNTL register bit definitions */
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54 #define CNTL_START 0x01
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55 #define CNTL_AUTO_RELOAD 0x02
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56 #define CNTL_CLOCK_ENABLE 0x20
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57
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58 #endif /* include guard */