FreeCalypso > hg > freecalypso-tools
annotate doc/SIM-hardware-debugging @ 483:e76cb6994508
CHANGES: first changes since fc-host-tools-r10
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 07 Mar 2019 01:42:18 +0000 |
parents | 10e168596dfd |
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doc/SIM-hardware-debugging: article written
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1 This article is only going to be of interest to those who are physically |
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2 producing Calypso-based hardware and therefore get to deal with the joys of |
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3 yield troubleshooting and failure analysis. If you are a mere user or software |
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4 developer working on known-good hardware made by someone other than you, then |
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5 none of the following applies to you. |
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6 |
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7 Testing the SIM interface on a Calypso device |
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8 ============================================= |
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9 |
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10 A basic pass/fail test of the SIM interface is quite straightforward: simply |
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11 insert a test SIM into the socket (at FreeCalypso hw manufacturing we currently |
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12 use Sysmocom SIMs for this purpose) and issue an AT+CFUN=1 command to the |
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13 standard firmware; if the SIM interface hardware is good, the command will |
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14 complete successfully with an OK response, otherwise it will throw up an error. |
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15 |
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16 But what do you do when this basic test fails? If you get a "SIM not inserted" |
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17 error even though the SIM *is* in fact inserted, how do you debug it further? |
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18 In order to facilitate lower-level debugging of SIM interface woes, we have |
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19 implemented a standalone simtest program described in this article. To run |
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20 this simtest program on your Calypso device, run an fc-iram command like this: |
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21 |
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22 fc-iram -h fcfam /dev/ttyXXX /opt/freecalypso/target-bin/simtest.srec |
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23 |
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24 Like other interactive programs in our target-utils suite, this simtest program |
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25 will present a '=' prompt for you to type further commands. The following |
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26 sequence of commands should bring up the SIM interface if the hardware is good: |
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27 |
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28 abbinit |
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29 volt 1.8 |
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30 setup |
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31 poll on |
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32 reset 1 |
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33 |
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34 You can change volt 1.8 to volt 3 if needed, but all recently made SIMs prefer |
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35 1.8 V and merely tolerate higher voltages. TI's Iota ABB chip, which is what |
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36 we target in FreeCalypso, does not support 5V SIMs - it doesn't have a charge |
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37 pump or any other boost converter to produce 5 V from lower battery voltages. |
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38 (It is not just TI but all mobile chipset vendors; it has been a very long time |
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39 since anyone made a phone that can power 5V SIMs, and any old 5V-only SIMs have |
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40 thus stopped being usable just as long ago.) |
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41 |
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42 If the hardware is good and you have a working SIM inserted in the socket as |
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43 you execute the above commands, you should see ATR bytes from your SIM appear |
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44 in your terminal window the moment you issue the last reset 1 command: that |
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45 final command transitions the SIM reset line from low to high, if the SIM has |
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46 been given good power and clock prior to this event, this transition causes it |
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47 to initialize and emit its Answer To Reset, and once you issue the poll on |
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48 command, our simtest programs listens for incoming bytes from the SIM at the |
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49 same time while it listens for you to type further commands. |
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50 |
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51 If you execute the above command sequence with a known-good SIM inserted in the |
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52 socket and you don't see any ATR bytes on the final reset 1 command, then you |
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53 have confirmed with a lower-level tool that your SIM interface hardware is |
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54 having some issues. Give it a poweroff command, rerun the fc-iram command to |
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55 get a fresh session, and get your oscilloscope ready. Now execute the commands |
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56 slowly, probing with your o'scope at each step: |
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57 |
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58 abbinit |
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59 volt 1.8 |
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60 |
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61 The volt command enables the VRSIM regulator in the Iota ABB chip and causes it |
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62 to put out the selected voltage. You should see this voltage appear on SIM |
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63 socket contact C1 (VCC); if it fails to appear there, then trace out the circuit |
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64 coming from VRSIM, and the VRSIM regulator itself (inside the chip) may also be |
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65 suspect. |
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66 |
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67 setup |
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68 |
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69 This command puts the SIM interface block inside the Calypso into a sensible |
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70 state and enables the SIM interface level shifters in the Iota ABB. After this |
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71 command you should see a good 3.25 MHz clock (13 MHz divided by 4) with selected |
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72 SIM voltage levels on the SIM CLK line (socket contact C3), the RST line (socket |
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73 contact C2) should be low, and the I/O line (socket contact C7) should be high. |
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74 The SIM clock is produced in the Calypso and then voltage-translated by a |
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75 unidirectional buffer in the Iota ABB, thus if the clock fails to appear at the |
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76 SIM socket, look for issues in that signal path. For the I/O line to be high |
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77 at this point in the bring-up sequence, the resistor pull-ups on both DBB-to-ABB |
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78 and ABB-to-socket sides need to be working; if the I/O line is high on the |
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79 DBB-to-ABB side and the pull-up on the ABB-to-socket side is good, but the I/O |
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80 line on the ABB-to-socket side is still low, then there may be something wrong |
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81 with the level shifter in the ABB holding it low. |
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82 |
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83 poll on |
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84 reset 1 |
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85 |
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86 (The poll on command can be omitted if you are doing o'scope probing on an empty |
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87 socket and thus not expecting any ATR.) As you issue that reset 1 command, hold |
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88 your oscilloscope probe on SIM socket contact C2, which is the RST line - it |
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89 should go from low to high. Our simtest utility's reset command (reset 0 or |
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90 reset 1) manipulates one bit in one Calypso register that controls the Calypso |
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91 chip's SIM_RST output, which then passes through a unidirectional level shifter |
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92 in the Iota ABB on its way to SIM socket contact C2. |
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93 |
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94 On those two FCDEV3B V2 boards that have been rejected as defective because of a |
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95 non-working SIM interface and which are now being revisited for a more thorough |
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96 investigation, we have not yet seen any problems with the SIM power supply |
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97 voltage, with the SIM CLK line or with the I/O line pull-up, but on both boards |
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98 the SIM RST line is not working: we see a constant low at socket contact C2 |
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99 (the only probe-able point in the entire SIM reset signal path), and reset 1 |
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100 produces no effect. Unfortunately there is no way to probe the DBBSRST signal |
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101 going from Calypso to Iota (it goes from one BGA to the other on an inner layer |
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102 without coming up to the surface except right under the two ball pads), thus it |
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103 is too difficult to tell where the breakage occurs: is it the Calypso failing |
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104 to put out a high on its SIM_RST output when commanded to do so by the register |
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105 setting, is it some fault in the PCB shorting this signal to GND before it |
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106 reaches Iota's DBBSRST input, is it some fault inside the Iota chip itself that |
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107 causes it to put out a low on its SIMRST output even though the DBBSRST input |
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108 is high, or is it some fault in the PCB shorting the ABB-to-socket SIM RST |
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109 output to GND? |
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110 |
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111 Given that FCDEV3B is not intended to be a high-volume product (we only need to |
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112 make enough good boards to provide one to every interested developer or |
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113 tinkerer), it will probably make more economic sense to simply reject SIM- |
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114 defective boards and write them off as a loss than to spend astronomical amounts |
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115 on PCB microsurgery to expose the DBBSRST signal for probing or other in-depth |
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116 troubleshooting measures along those lines. For future board designs that may |
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117 need to be produced in higher volumes, the Mother's current plan is to add |
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118 probe-able test points on DBBSCK and DBBSRST lines, so that if similar problems |
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119 recur, we'll be able to quickly isolate them to the Calypso side or the Iota |
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120 side. |