FreeCalypso > hg > freecalypso-tools
annotate target-utils/include/simregs.h @ 836:f7e946389f8b
tiaud-compile: add support for aec-new
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Fri, 30 Jul 2021 00:50:47 +0000 |
parents | 4e6837859c0b |
children |
rev | line source |
---|---|
454
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
1 /* Calypso SIM registers definition */ |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
2 |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
3 #define SIM_BASE_ADDR 0xFFFE0000 |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
4 |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
5 struct sim_registers { |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
6 u16 cmd; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
7 u16 stat; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
8 u16 conf1; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
9 u16 conf2; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
10 u16 it; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
11 u16 drx; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
12 u16 dtx; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
13 u16 maskit; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
14 u16 it_cd; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
15 }; |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
16 |
daaab2701761
target-utils: simtest program started
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff
changeset
|
17 #define SIMREGS (*(volatile struct sim_registers *) SIM_BASE_ADDR) |
457
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
18 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
19 /* |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
20 * Bit definitions |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
21 */ |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
22 // control regidter |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
23 #define SIM_CMD_CRST 0x0001 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
24 #define SIM_CMD_SWRST 0x0002 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
25 #define SIM_CMD_STOP 0x0004 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
26 #define SIM_CMD_START 0x0008 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
27 #define SIM_CMD_CLKEN 0x0010 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
28 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
29 // status register |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
30 #define SIM_STAT_CD 0x0001 // card present |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
31 #define SIM_STAT_TXPAR 0x0002 // transmit parity status |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
32 #define SIM_STAT_FFULL 0x0004 // fifo full |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
33 #define SIM_STAT_FEMPTY 0x0008 // fifo empty |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
34 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
35 // configuration register |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
36 #define SIM_CONF1_CHKPAR 0x0001 // enable receipt check parity |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
37 #define SIM_CONF1_CONV 0x0002 // coding convention |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
38 #define SIM_CONF1_TXRX 0x0004 // SIO line direction |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
39 #define SIM_CONF1_SCLKEN 0x0008 // enable SIM clock |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
40 #define SIM_CONF1_RSVD 0x0010 // reserved |
767
6717f18780d8
target-utils/simtest/simregs.h: a little white space fix
Mychaela Falconia <falcon@freecalypso.org>
parents:
457
diff
changeset
|
41 #define SIM_CONF1_SCLKDIV 0x0020 // SIM clock frquency |
6717f18780d8
target-utils/simtest/simregs.h: a little white space fix
Mychaela Falconia <falcon@freecalypso.org>
parents:
457
diff
changeset
|
42 #define SIM_CONF1_SCLKLEV 0x0040 // SIM clock idle level |
457
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
43 #define SIM_CONF1_ETU 0x0080 // ETU period |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
44 #define SIM_CONF1_BYPASS 0x0100 // bypass hardware timers |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
45 #define SIM_CONF1_SVCCLEV 0x0200 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
46 #define SIM_CONF1_SRSTLEV 0x0400 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
47 #define SIM_CONF1_SIOLOW 0x8000 //force SIO to low level |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
48 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
49 // interrupt status register |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
50 #define SIM_IT_NATR 0x0001 // No answer to reset |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
51 #define SIM_IT_WT 0x0002 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
52 #define SIM_IT_ITOV 0x0004 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
53 #define SIM_IT_ITTX 0x0008 // Transmit |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
54 #define SIM_IT_ITRX 0x0010 // Receipt |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
55 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
56 #define SIM_IT_CD 0x0001 // Card insertion/extraction |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
57 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
58 // interrupt mask register |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
59 #define SIM_MASK_NATR 0x0001 // No answer to reset |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
60 #define SIM_MASK_WT 0x0002 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
61 #define SIM_MASK_OV 0x0004 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
62 #define SIM_MASK_TX 0x0008 // Transmit |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
63 #define SIM_MASK_RX 0x0010 // Receipt |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
64 #define SIM_MASK_CD 0x0020 // Card insertion/extraction |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
65 |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
66 // receveid byte register |
d96ea6ae6aa5
simtest: setup implemented
Mychaela Falconia <falcon@freecalypso.org>
parents:
454
diff
changeset
|
67 #define SIM_DRX_STATRXPAR 0x0100 // received byte parity status |