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annotate doc/Loadtool-flash-support @ 619:f82551c77e58

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libserial-newlnx: ASYNC_LOW_LATENCY patch reverted Reports from Das Signal indicate that loadtools performance on Debian is about the same as on Slackware, and that including or omitting the ASYNC_LOW_LATENCY patch from Serg makes no difference. Because the patch in question does not appear to be necessary, it is being reverted until and unless someone other than Serg reports an actual real-world system on which loadtools operation times are slowed compared to the Mother's Slackware reference and on which Slackware-like performance can be restored by setting the ASYNC_LOW_LATENCY flag.
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 27 Feb 2020 01:09:48 +0000
parents 809829dbc58a
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1 fc-loadtool is our tool for reading and writing the non-volatile flash memory
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2 on all of our supported target devices, and the set of targets which it needs
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3 to support keeps growing. Here are some of the challenges we have to deal with:
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4
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5 * Some Calypso board designs use AMD-style flash, others use Intel-style flash.
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6 Initially we only supported AMD-style flash chips that were used in our first
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7 targets (Openmoko GTA02 and Pirelli DP-L10), then we got other targets that
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8 have Intel-style flash. So far we have not yet run into a case where both
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9 kinds of flash can be encountered on the same target family, but our current
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10 design supports this possibility.
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11
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12 * All Calypso devices which we currently support have flash chips with non-
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13 uniform sector geometries, i.e., the area that would otherwise be the first
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14 or the last sector is subdivided into smaller sectors (erase units). Both
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15 "top boot" (small sectors at high addresses) and "bottom boot" (small sectors
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16 at low addresses) geometries are found among our targets, as well as flashes
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17 that have small sectors at both ends. The exact sector geometry needs to be
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18 known to the flash manipulation tool in order to perform correct flash erase
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19 and program operations.
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20
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21 * While most Calypso devices have a single flash chip providing a single bank
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22 of flash (can be as small as 2 MiB or as big as 8 MiB), some of our targets
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23 (our own FCDEV3B and the Pirelli DP-L10 phone from which the idea was copied)
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24 provide two flash chip select banks of 8 MiB each. To make the matters even
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25 more complicated, all of that flash is actually a single 16 MiB chip that has
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26 two chip selects instead of one, specifically designed for processors like
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27 our Calypso that can only address a maximum of 8 MiB per chip select.
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28
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29 * It is a fixed target property whether a given board is wired for only one
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30 flash chip select or allows the possibility of dual-bank flash, and if a
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31 second flash chip select is provided for, which Calypso chip select it is
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32 wired to.
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33
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34 Given the existence of the CFI (Common Flash Interface) standard and the fact
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35 that every flash chip we have encountered so far in a Calypso device does have
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36 a readable CFI structure, one may naively think that the most sensible way to
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37 support all of our possible flash configurations would be to read and parse the
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38 CFI structure in a device-agnostic way (i.e., without special cases for specific
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39 chip types) and thus support "everything". But here are the problems with this
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40 simplistic approach:
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41
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42 * On boards that have 16 MiB of flash in a Spansion S71PL129J or S71PL129N chip,
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43 it makes the most sense for us to treat this big flash as two separate banks
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44 of 8 MiB each - but the CFI structure describes a single 16 MiB flash chip.
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45
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46 * AMD-style flashes with "top boot" geometries are among our repertoire of
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47 devices to be supported, and they have their regions listed in the wrong order
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48 in the CFI structure - one needs to look in the AMD-specific part outside of
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49 the vendor-neutral geometry structure to see the true "top boot" geometry.
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50
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51 * Intel-style flashes with independent read/write partitions such that each
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52 partition has its own status register and its own "read array" vs. "read SR"
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53 state require special handling in our architecture, but autoconfiguring this
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54 quirk agnostically from CFI seems too difficult to me, and I wouldn't trust
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55 it.
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56
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57 Our previous architectural attempts
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58 ===================================
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59
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60 Initially we only supported two flash chip types, Samsung K5A32xx_T (Openmoko
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61 GTA02) and Spansion S71PL129N (Pirelli DP-L10) with strictly manual selection:
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62 -h gta02 selected one and -h pirelli selected the other via hardware parameter
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63 files. There was an ID check to prevent bogosity from wrong manual selection,
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64 but no autodetection or autoconfiguration. Then we added Compal target support;
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65 aside from Mot C155/156 which has partition quirks that were only discovered
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66 much later, these phones have simple Intel-style flashes without any of the CFI
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67 problems listed above, thus they were handled via CFI. Thus we had a hybrid
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68 architecture: Openmoko, Pirelli and FCDEV3B targets were handled by way of
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69 manual selection and ID checks to catch errors, whereas Compal targets were
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70 handled by way of CFI-based autodetection and autoconfiguration.
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71
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72 Then it was discovered that the 8 MiB Intel-style flash on the D-Sample board
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73 and on Mot C155/156 has partition quirks which our CFI-based autoconfiguration
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74 (looking at vendor-agnostic geometry bits only) could not take care of, and the
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75 solution was to move these targets from CFI-based autoconfiguration to the same
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76 kind of fixed device selection and configuration as was used for AMD flashes.
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77 At that point our flash handling architecture became a mess, and when I started
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78 questioning how to extend it further as the need arises to support more
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79 different flash chip types on a wide variety of Calypso targets, it became
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80 clear that a redesign was needed.
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81
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82 Our current architecture
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83 ========================
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84
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85 In our current architecture the only flash configuration that is indicated
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86 statically in the hardware parameter files (selected with the -h option,
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87 practically meaning predefined target configurations) is board wiring
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88 information. There are 3 possibilities that can be configured:
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89
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90 flash single-4M base_addr -- wired for 1 bank of up to 4 MiB
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91 flash single-8M base_addr -- wired for 1 bank of up to 8 MiB
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92 flash dual-8M bank0_base bank1_base -- wired for 2 banks of up to 8 MiB each
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93
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94 Naturally the dual-8M configuration only makes sense for boards that are wired
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95 with a provision for a second flash bank, in which case the second bank base
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96 address will depend on the board wiring, i.e., which Calypso chip select it is.
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97 (Bank 0 base address will normally be 0x03000000, i.e., the alternate nCS0
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98 mapping that needs to be used when the boot ROM is mapped at 0.) The choice
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99 between single-4M and single-8M needs to match whether or not the associated
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100 init script includes a "w16 fffef006 0008" command to enable ADD22.
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101
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102 Beyond this board wiring configuration, the rest of flash support is based on a
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103 hard-coded table of all supported devices (a table that can grow indefinitely)
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104 plus autodetection amongst this supported set. In other words, fc-loadtool will
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105 only operate on a given flash chip if it explicitly knows about that chip, but
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106 the set of supported chips can be indefinitely extended without hitting
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107 architectural barriers, and our autodetection logic will detect and handle any
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108 supported chip on any board target.
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109
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110 Autodetection details
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111 =====================
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112
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113 The flash chip autodetection operation proceeds as follows:
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114
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115 * A sequence of writes is done to put the chip into the Read ID mode,
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116 equivalent to the following hypothetical C code with base_addr being an
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117 integer:
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118
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119 *(volatile uint16_t *)(base_addr + 0xAAA) = 0xAA;
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120 *(volatile uint16_t *)(base_addr + 0x554) = 0x55;
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121 *(volatile uint16_t *)(base_addr + 0xAAA) = 0x90;
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122
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123 * 16-bit words at base_addr offsets of 0 and 2 (where the manufacturer and
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124 device ID codes are expected to reside) are read, and this ID is looked up in
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125 a table. If the ID code is not known, we give up and don't allow any flash
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126 operations.
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127
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128 * For most ID codes, if we have found the code in our table, we know what device
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129 we should expect. But before we go ahead and assume that the command set and
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130 the geometry are as we think based on the ID code, we also do a CFI check.
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131 Specifically, we put the flash chip into CFI query mode, read a defined set
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132 of word locations (can be different for each chip type), and require these
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133 words to match our compiled-in table. Thus we guard against the possibility
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134 of some other flash chip having the same ID code (yes, there are known
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135 instances of ID code reuse) but having a different geometry.
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136
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137 * Some ID codes receive more complex handling. Right now the only such case is
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138 Spansion PL-J/PL-N flash. PL129J and PL129N flashes have different geometries
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139 and thus must be distinguished, but they have exactly the same ID codes and
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140 can only be distinguished by CFI. We have CFI match tables for PL129J and
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141 for PL129N; we try to match the CFI bits provided by the chip against one
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142 table first, and if it fails to match, we try the other. (As an optimization,
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143 we try the PL129N table first, as the N flash is the one found in real-world
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144 Pirelli DP-L10 specimen and used on our FCDEV3B.) If the CFI matches neither
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145 table, we give up and don't allow any flash operations.
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146
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147 The end effect of this logic is that we err on the side of caution: we only
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148 allow flash erase and program operations if we detect a flash chip which is
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149 fully known to us and fully matches our expectations, with both the ID codes
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150 and the CFI structure being as we expect.
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151
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152 Adding support for new flash chip types
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153 =======================================
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154
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155 All supported flash devices are listed in the fldevs.c source module; new
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156 devices that differ in geometry, command set or quirks need to be added there.
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157 The description of each flash device in fldevs.c also includes the CFI table
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158 that needs to matched to confirm the device in question. A different module
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159 named flashid.c contains the autodetection function and the table of device ID
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160 codes; the latter table always needs to be extended, sometimes adding an
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161 entirely new device, othertimes adding a newly found ID code for some flash
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162 chip that is fully equivalent to an already supported one in terms of geometry,
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163 command set and relevant quirks.
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164
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165 What do you do if you are an end user (not a FreeCalypso developer) and you got
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166 a Calypso device whose flash chip is not being recognized by fc-loadtool?
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167 Answer: you send the output of the "flash id" command (contains ID codes) and a
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168 dump of the CFI structure to Mother Mychaela for analysis. To make a dump of
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169 the CFI structure, execute the following commands:
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170
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171 loadtool> w16 030000aa 98
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172 loadtool> dump2bin 03000000 200 cfidump.bin
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173
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174 Handling of dual-bank 16 MiB flash chips
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175 ========================================
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176
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177 The Calypso can only address a maximum of 8 MiB per chip select, thus 16 MiB or
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178 larger flash chips with a single chip select cannot be used in Calypso board
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179 designs. However, there are some special 16 MiB flash chips that present
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180 themselves as two banks of 8 MiB each (even though the CFI structure describes
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181 a single 16 MiB chip), and such flash chips are used on the Pirelli DP-L10 and
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182 on our own FCDEV3B.
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183
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184 The flash handling architecture of fc-loadtool allows two banks to be configured
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185 via a flash dual-8M setting in the hardware parameter file, and when that
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186 configuration is used (-h fcfam and -h pirelli), the two banks are treated as
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187 being entirely independent. All regular flash commands operate only on the main
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188 bank, and a parallel set of flash2 commands operates on the secondary bank.
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189 The autodetection logic and the resulting configuration are done independently
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190 on each flash bank when it is first accessed, thus fc-loadtool would happily
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191 handle two separate flash chips of different types, even though such arrangement
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192 is not expected to occur in any Calypso device. But when a PL129J or PL129N
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193 device is detected (the two dual-bank devices we currently support) on the
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194 autodetection probe of either bank, the operating geometry is configured
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195 appropriately based on which bank it is.
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196
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197 Primary flash bank mapping at 0x03000000
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198 ========================================
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199
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200 When loadagent runs on the Calypso target controlled by fc-loadtool, the Calypso
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201 boot ROM will usually be mapped at 0, thus the alternate nCS0 mapping at
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202 0x03000000 needs to be used for flash access. However, the Calypso chip (all
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203 versions we work with) has a little design bug in this part of the silicon:
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204 this alternate nCS0 mapping at 0x03000000 works only when the debug visibility
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205 bit in the API-RHEA control register (bit 6 in the FFFF:FB0E register) is set,
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206 and does not work otherwise. This bit is initially set as the Calypso comes
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207 out of reset, and on most platforms we gain loadtool access via the boot ROM,
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208 hence the problem does not occur - but on Compal targets we gain loadtool
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209 access either through Compal's bootloader or via tfc139, and in both cases
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210 Compal's fw (either the full fw or the bootloader part) has already set the
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211 register in question to the runtime operational value of 0x2A (unchanged from
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212 TI's TCS211 reference fw), with the debug visibility bit cleared, hence the
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213 0x03000000 flash mapping no longer works.
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214
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215 There are two possible solutions: we can write into the FFFF:FB10 register to
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216 disable the boot ROM and use the "regular" flash mapping at 0, which is what we
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217 used to do, or we can write into the FFFF:FB0E register and re-enable the debug
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218 visibility mode. Right now we do the latter, allowing us to use the same
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219 0x03000000 flash mapping on all targets for consistency.