FreeCalypso > hg > freecalypso-tools
annotate loadtools/scripts/compal.config @ 1014:961efadd530a default tip
fc-shell TCH DL handler: add support for CSD modes
TCH DL capture mechanism in FC Tourmaline firmware has been extended
to support CSD modes in addition to speech - add the necessary support
on the host tools side.
It needs to be noted that this mechanism in its present state does NOT
provide the debug utility value that was sought: as we learned only
after the code was implemented, TI's DSP has a misfeature in that the
buffer we are reading (a_dd_0[]) is zeroed out when the IDS block
is enabled, i.e., we are reading all zeros and not the real DL bits
we were after. But since the code has already been written, we are
keeping it - perhaps we can do some tests with IDS disabled.
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 26 Nov 2024 06:27:43 +0000 |
parents | b0f9d38bfd9e |
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loadtools/scripts/*.config: new flash config
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1 # This configuration is intended to be applicable to all of C11x, C12x, |
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2 # C139 and C140. The "plain" version of compalstage selected below |
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3 # should work for all C11x/12x; it will also work on C139/140 phones |
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4 # that had the simpler boot code flashed into them, as we do with |
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5 # FreeCalypso fw on these phones. When running loadtools with this config |
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6 # on C139/140 phones that still have the official fw in them, one will need |
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7 # to specify -h compal -c 1004 to use the inefficient ~15 KiB version of |
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8 # compalstage. |
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9 |
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10 compal-stage plain |
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11 |
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12 # Whether we are breaking in through compalstage (as above) or through |
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13 # tfc139, the re-enabled Calypso boot ROM is used to load our loadagent |
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14 # into IRAM. The boot ROM will autodetect the Calypso input clock as |
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15 # 26 MHz (physical reality) when entered through compalstage, or as |
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16 # 13 MHz when entered through tfc139 - the latter results from the |
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17 # original fw setting bit 7 in the FFFF:FD02 register (VTCXO_DIV2), |
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18 # which the boot ROM does not clear. |
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19 # |
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20 # However, the following configuration will result in the ARM core |
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21 # being clocked at 52 MHz in both cases. |
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22 |
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23 pll-config 4/1 |
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24 rhea-cntl 0x00 |
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25 |
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26 # The remaining settings are carried out via loadagent commands |
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27 init-script compal.init |
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28 |
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29 # Flash can be 2 MiB or 4 MiB, will be autodetected, 4 MiB mapping used |
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30 # mapped at 0x03000000 like on other targets, see updated compal.init script |
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31 flash single-4M 0x03000000 |
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32 |
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33 boot-reflash-hack 0x820000 0x10000 |
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34 |
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35 # Perform a Iota poweroff when we are done |
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36 exit-mode iota-off |