FreeCalypso > hg > freecalypso-tools
comparison target-utils/calversion/dsp_const.h @ 441:1dcc9e4b71fd
target-utils/calversion: program written, compiles
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Wed, 26 Dec 2018 06:40:02 +0000 |
parents | |
children |
comparison
equal
deleted
inserted
replaced
440:44f73d56b6f5 | 441:1dcc9e4b71fd |
---|---|
1 /* | |
2 * This header file is a subset of l1_const.h from TCS211, defining | |
3 * those constants which are needed for the DSP bring-up code in | |
4 * the dsp_bringup.c module. | |
5 */ | |
6 | |
7 #define NO_PAR 0 | |
8 | |
9 #define NO_TASK 0 | |
10 #define ALL_TASK 0xffffffff | |
11 #define ALL_PARAM 0xffffffff | |
12 | |
13 #define TRUE 1 | |
14 #define TRUE_L 1L | |
15 #define FALSE 0 | |
16 | |
17 #define NOT_PENDING 0 | |
18 #define PENDING 1 | |
19 | |
20 #define INACTIVE 2 | |
21 #define ACTIVE 3 | |
22 #define RE_ENTERED 4 | |
23 #define WAIT_IQ 5 | |
24 | |
25 //--------------------------------------------- | |
26 // MCU-DSP bit-field bit position definitions | |
27 //--------------------------------------------- | |
28 #define GPRS_SCHEDULER 1 // Select GPRS scheduler | |
29 #define GSM_SCHEDULER 2 // Select GSM scheduler | |
30 | |
31 // DSP state need to be used to enter Deep Sleep mode | |
32 #define C_DSP_IDLE3 3 | |
33 | |
34 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800))) | |
35 | |
36 // **************************************************************** | |
37 // PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS | |
38 // **************************************************************** | |
39 #define C_POND_RED 1L | |
40 #define D_NSUBB_IDLE 296L | |
41 #define D_NSUBB_DEDIC 30L | |
42 #define D_FB_THR_DET_IACQ 0x3333L | |
43 #define D_FB_THR_DET_TRACK 0x28f6L | |
44 #define D_DC_OFF_THRES 0x7fffL | |
45 #define D_DUMMY_THRES 17408L | |
46 #define D_DEM_POND_GEWL 26624L | |
47 #define D_DEM_POND_RED 20152L | |
48 #define D_HOLE 0L | |
49 #define D_TRANSFER_RATE 0x6666L | |
50 | |
51 // Full Rate vocoder definitions. | |
52 #define D_MACCTHRESH1 7872L | |
53 #define D_MLDT -4L | |
54 #define D_MACCTHRESH 7872L | |
55 #define D_GU 5772L | |
56 #define D_GO 7872L | |
57 #define D_ATTMAX 53L | |
58 #define D_SM -892L | |
59 #define D_B 208L | |
60 #define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED) | |
61 #define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED) | |
62 #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED) | |
63 #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED) | |
64 | |
65 // Frequency burst definitions | |
66 #define D_FB_MARGIN_BEG 24 | |
67 #define D_FB_MARGIN_END 22 | |
68 | |
69 // V42bis definitions | |
70 #define D_V42B_SWITCH_HYST 16L | |
71 #define D_V42B_SWITCH_MIN 64L | |
72 #define D_V42B_SWITCH_MAX 250L | |
73 #define D_V42B_RESET_DELAY 10L | |
74 | |
75 #define D_LAT_MCU_BRIDGE 0x000FL | |
76 | |
77 #define D_LAT_MCU_HOM2SAM 0x000CL | |
78 | |
79 #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L | |
80 #define D_LAT_DSP_AFTER_SAM 0x0004L | |
81 | |
82 // Background Task in GSM mode: Initialization. | |
83 #define D_GSM_BGD_MGT 0L | |
84 | |
85 #define D_MISC_CONFIG 1L | |
86 | |
87 // Half Rate vocoder and ched definitions. | |
88 | |
89 #define D_SD_MIN_THR_TCHHS 37L | |
90 #define D_MA_MIN_THR_TCHHS 344L | |
91 #define D_MD_MAX_THR_TCHHS 2175L | |
92 #define D_MD1_MAX_THR_TCHHS 138L | |
93 #define D_SD_AV_THR_TCHHS 1845L | |
94 #define D_WED_FIL_TC 0x7c00L | |
95 #define D_WED_FIL_INI 4650L | |
96 #define D_X_MIN 15L | |
97 #define D_X_MAX 23L | |
98 #define D_Y_MIN 703L | |
99 #define D_Y_MAX 2460L | |
100 #define D_SLOPE 135L | |
101 #define D_WED_DIFF_THRESHOLD 406L | |
102 #define D_MABFI_MIN_THR_TCHHS 5320L | |
103 #define D_LDT_HR -5 | |
104 #define D_MACCTRESH_HR 6500 | |
105 #define D_MACCTRESH1_HR 6500 | |
106 #define D_GU_HR 2620 | |
107 #define D_GO_HR 3700 | |
108 #define D_B_HR 182 | |
109 #define D_SM_HR -1608 | |
110 #define D_ATTMAX_HR 53 | |
111 | |
112 // Enhanced Full Rate vocoder and ched definitions. | |
113 | |
114 #define C_MLDT_EFR -4 | |
115 #define C_MACCTHRESH_EFR 8000 | |
116 #define C_MACCTHRESH1_EFR 8000 | |
117 #define C_GU_EFR 4522 | |
118 #define C_GO_EFR 6500 | |
119 #define C_B_EFR 174 | |
120 #define C_SM_EFR -878 | |
121 #define C_ATTMAX_EFR 53 | |
122 #define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED) | |
123 #define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED) | |
124 #define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED) | |
125 #define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED) | |
126 | |
127 // Integrated Data Services definitions. | |
128 #define D_MAX_OVSPD_UL 8 | |
129 // Detect frames containing 90% of 1s as synchro frames | |
130 #define D_SYNC_THRES 0x3f50 | |
131 // IDLE frames are only frames with 100 % of 1s | |
132 #define D_IDLE_THRES 0x4000 | |
133 #define D_M1_THRES 5 | |
134 #define D_MAX_OVSP_DL 8 | |
135 | |
136 #define D_FACCH_THR 0 | |
137 #define D_DSP_TEST 0 | |
138 #define D_VERSION_NUMBER 0 | |
139 #define D_TI_VERSION 0 | |
140 | |
141 // DSP ADRESSES | |
142 //-------------------- | |
143 | |
144 #define DB_SIZE (4*20L) // 4 pages of 20 words... | |
145 | |
146 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long | |
147 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long | |
148 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long | |
149 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long | |
150 #define NDB_ADR 0xFFD001A8L // NDB start address : 268 words | |
151 #define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words | |
152 | |
153 #define DB2_R_PAGE_0 0xFFD00184L | |
154 #define DB2_R_PAGE_1 0xFFD00188L |