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comparison target-utils/calversion/dsp_defty.h @ 441:1dcc9e4b71fd

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target-utils/calversion: program written, compiles
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 26 Dec 2018 06:40:02 +0000
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440:44f73d56b6f5 441:1dcc9e4b71fd
1 /*
2 * This header file is a stripped-down version of l1_defty.h from TCS211,
3 * defining the DSP's API RAM shared memory interface.
4 */
5
6 typedef unsigned short API;
7 typedef signed short API_SIGNED;
8
9 typedef struct
10 {
11 API d_task_d; // (0) Downlink task command.
12 API d_burst_d; // (1) Downlink burst identifier.
13 API d_task_u; // (2) Uplink task command.
14 API d_burst_u; // (3) Uplink burst identifier.
15 API d_task_md; // (4) Downlink Monitoring (FB/SB) command.
16 API d_background; // (5) Background tasks
17 API d_debug; // (6) Debug/Acknowledge/general purpose word.
18 API d_task_ra; // (7) RA task command.
19 API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only.
20 // bit [0..7] -> b_fn_report, FN in the normalized reporting period.
21 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning.
22 API d_ctrl_tch; // (9) Tch channel description.
23 // bit [0..3] -> b_chan_mode, channel mode.
24 // bit [4..5] -> b_chan_type, channel type.
25 // bit [6] -> reset SACCH
26 // bit [7] -> vocoder ON
27 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL.
28 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL.
29 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
30 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
31 // bit [12.13] -> b_tch_loop, tch loops A/B/C.
32 API hole; // (10) unused hole.
33
34 API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send.
35 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB
36 // bit [1.2] -> unused
37 // bit [3] -> b_apcdel: delays-register in NDB
38 // bit [4] -> b_afc: freq control register in DB
39 // bit [5..15] -> unused
40 API a_a5fn[2]; // (12..13) Encryption Frame number.
41 // word 0, bit [0..4] -> T2.
42 // word 0, bit [5..10] -> T3.
43 // word 1, bit [0..11] -> T1.
44 API d_power_ctl; // (14) Power level control.
45 API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb").
46 API d_ctrl_system; // (16) Controle Register for RESET/RESUME.
47 // bit [0..2] -> b_tsq, training sequence.
48 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication.
49 // bit [15] -> b_task_abort, DSP task abort command.
50 }
51 T_DB_MCU_TO_DSP;
52
53 typedef struct
54 {
55 API d_task_d; // (0) Downlink task command.
56 API d_burst_d; // (1) Downlink burst identifier.
57 API d_task_u; // (2) Uplink task command.
58 API d_burst_u; // (3) Uplink burst identifier.
59 API d_task_md; // (4) Downlink Monitoring (FB/SB) task command.
60 API d_background; // (5) Background tasks
61 API d_debug; // (6) Debug/Acknowledge/general purpose word.
62 API d_task_ra; // (7) RA task command.
63
64 API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
65 API a_pm[3]; // (12..14) Power measurement results, array of 3 words.
66 API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
67 }
68 T_DB_DSP_TO_MCU;
69
70 typedef struct
71 {
72 // MISC Tasks
73 API d_dsp_page;
74
75 // DSP status returned (DSP --> MCU).
76 API d_error_status;
77
78 // RIF control (MCU -> DSP).
79 API d_spcx_rif;
80
81 API d_tch_mode; // TCH mode register.
82 // bit [0..1] -> b_dai_mode.
83 // bit [2] -> b_dtx.
84
85 API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega
86
87 API d_dsp_test;
88
89 // Words dedicated to Software version (DSP code + Patch)
90 API d_version_number1;
91 API d_version_number2;
92
93 API d_debug_ptr;
94 API d_debug_bk;
95
96 API d_pll_config;
97
98 // GSM/GPRS DSP Debug trace support
99 API p_debug_buffer;
100 API d_debug_buffer_size;
101 API d_debug_trace_type;
102
103 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
104 API d_dsp_state;
105 // 5 words are reserved for any possible mapping modification
106 API d_hole1_ndb[2];
107
108 API p_debug_amr;
109
110 API d_hole2_ndb[1];
111 API d_mcsi_select;
112
113 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
114 API d_apcdel1_bis;
115 API d_apcdel2_bis;
116
117 // New registers due to IOTA analog base band
118 API d_apcdel2;
119 API d_vbctrl2;
120 API d_bulgcal;
121
122 // Analog Based Band
123 API d_afcctladd;
124
125 API d_vbuctrl;
126 API d_vbdctrl;
127 API d_apcdel1;
128 API d_apcoff;
129 API d_bulioff;
130 API d_bulqoff;
131 API d_dai_onoff;
132 API d_auxdac;
133
134 API d_vbctrl1;
135
136 API d_bbctrl;
137
138 // Monitoring tasks control (MCU <- DSP)
139 // FB task
140 API d_fb_det; // FB detection result. (1 for FOUND).
141 API d_fb_mode; // Mode for FB detection algorithm.
142 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
143
144 // SB Task
145 API a_sch26[5]; // Header + SB information, array of 5 words.
146
147 API d_audio_gain_ul;
148 API d_audio_gain_dl;
149
150 // Controller of the melody E2 audio compressor
151 API d_audio_compressor_ctrl;
152
153 // AUDIO module
154 API d_audio_init;
155 API d_audio_status;
156
157 // Audio tasks
158 // TONES (MCU -> DSP)
159 API d_toneskb_init;
160 API d_toneskb_status;
161 API d_k_x1_t0;
162 API d_k_x1_t1;
163 API d_k_x1_t2;
164 API d_pe_rep;
165 API d_pe_off;
166 API d_se_off;
167 API d_bu_off;
168 API d_t0_on;
169 API d_t0_off;
170 API d_t1_on;
171 API d_t1_off;
172 API d_t2_on;
173 API d_t2_off;
174 API d_k_x1_kt0;
175 API d_k_x1_kt1;
176 API d_dur_kb;
177 API d_shiftdl;
178 API d_shiftul;
179
180 API d_aec_ctrl;
181
182 API d_es_level_api;
183 API d_mu_api;
184
185 // Melody Ringer module
186 API d_melo_osc_used;
187 API d_melo_osc_active;
188 API a_melo_note0[4];
189 API a_melo_note1[4];
190 API a_melo_note2[4];
191 API a_melo_note3[4];
192 API a_melo_note4[4];
193 API a_melo_note5[4];
194 API a_melo_note6[4];
195 API a_melo_note7[4];
196
197 // selection of the melody format
198 API d_melody_selection;
199
200 // Holes due to the format melody E1
201 API a_melo_holes[3];
202
203 // Speech Recognition module
204 API d_sr_status; // status of the DSP speech reco task
205 API d_sr_param; // paramters for the DSP speech reco task: OOV threshold.
206 API d_sr_bit_exact_test; // bit exact test
207 API d_sr_nb_words; // number of words used in the speech recognition task
208 API d_sr_db_level; // estimate voice level in dB
209 API d_sr_db_noise; // estimate noise in dB
210 API d_sr_mod_size; // size of the model
211 API a_n_best_words[4]; // array of the 4 best words
212 API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length)
213
214 // Audio buffer
215 API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1.
216 API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1.
217
218 // V42bis module
219 API d_v42b_nego0;
220 API d_v42b_nego1;
221 API d_v42b_control;
222 API d_v42b_ratio_ind;
223 API d_mcu_control;
224 API d_mcu_control_sema;
225
226 // Background tasks
227 API d_background_enable;
228 API d_background_abort;
229 API d_background_state;
230 API d_max_background;
231 API a_background_tasks[16];
232 API a_back_task_io[16];
233
234 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
235 API d_gea_mode_ovly;
236 API a_gea_kc_ovly[4];
237
238 // SYREN specific registers
239 API d_vbpop;
240 API d_vau_delay_init;
241 API d_vaud_cfg;
242 API d_vauo_onoff;
243 API d_vaus_vol;
244 API d_vaud_pll;
245 API d_hole3_ndb[1];
246
247 // word used for the init of USF threshold
248 API d_thr_usf_detect;
249
250 // Encryption module
251 API d_a5mode; // Encryption Mode.
252
253 API d_sched_mode_gprs_ovly;
254
255 // 7 words are reserved for any possible mapping modification
256 API d_hole4_ndb[5];
257
258 // Ramp definition for Omega device
259 API a_ramp[16];
260
261 // CCCH/SACCH downlink information...(!!)
262 API a_cd[15]; // Header + CCCH/SACCH downlink information.
263
264 // FACCH downlink information........(!!)
265 API a_fd[15]; // Header + FACCH downlink information.
266
267 // Traffic downlink data frames......(!!)
268 API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0.
269
270 // CCCH/SACCH uplink information.....(!!)
271 API a_cu[15]; // Header + CCCH/SACCH uplink information.
272
273 // FACCH downlink information........(!!)
274 API a_fu[15]; // Header + FACCH uplink information
275
276 // Traffic downlink data frames......(!!)
277 API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0.
278
279 // Random access.....................(MCU -> DSP).
280 API d_rach; // RACH information.
281
282 //...................................(MCU -> DSP).
283 API a_kc[4]; // Encryption Key Code.
284
285 // Integrated Data Services module
286 API d_ra_conf;
287 API d_ra_act;
288 API d_ra_test;
289 API d_ra_statu;
290 API d_ra_statd;
291 API d_fax;
292 API a_data_buf_ul[21];
293 API a_data_buf_dl[37];
294
295 // GTT API mapping for DSP code 34 (for test only)
296 API d_tty_status;
297 API d_tty_detect_thres;
298 API d_ctm_detect_shift;
299 API d_tty_fa_thres;
300 API d_tty_mod_norm;
301 API d_tty_reset_buffer_ul;
302 API d_tty_loop_ctrl;
303 API p_tty_loop_buffer;
304
305 API a_sr_holes0[414];
306
307 // new AEC
308 API d_cont_filter;
309 API d_granularity_att;
310 API d_coef_smooth;
311 API d_es_level_max;
312 API d_fact_vad;
313 API d_thrs_abs;
314 API d_fact_asd_fil;
315 API d_fact_asd_mut;
316 API d_far_end_pow_h;
317 API d_far_end_pow_l;
318 API d_far_end_noise_h;
319 API d_far_end_noise_l;
320
321 // Speech recognition model
322 API a_sr_holes1[145];
323 API d_cport_init;
324 API d_cport_ctrl;
325 API a_cport_cfr[2];
326 API d_cport_tcl_tadt;
327 API d_cport_tdat;
328 API d_cport_tvs;
329 API d_cport_status;
330 API d_cport_reg_value;
331
332 API a_cport_holes[1011];
333
334 API a_model[1041];
335
336 // EOTD buffer
337 API d_eotd_first;
338 API d_eotd_max;
339 API d_eotd_nrj_high;
340 API d_eotd_nrj_low;
341 API a_eotd_crosscor[18];
342 // AMR ver 1.0 buffers
343 API a_amr_config[4];
344 API a_ratscch_ul[6];
345 API a_ratscch_dl[6];
346 API d_amr_snr_est; // estimation of the SNR of the AMR speech block
347 API d_amms_ul_voc;
348 API d_thr_onset_afs; // thresh detection ONSET AFS
349 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
350 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
351 API d_thr_update_afs; // thresh detection SID_UPDATE AFS
352 API d_thr_onset_ahs; // thresh detection ONSET AHS
353 API d_thr_sid_ahs; // thresh detection SID frames AHS
354 API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER
355 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
356 API d_thr_soft_bits;
357
358 API d_melody_e2_osc_stop;
359 API d_melody_e2_osc_active;
360 API d_melody_e2_semaphore;
361 API a_melody_e2_osc[16][3];
362 API d_melody_e2_globaltimefactor;
363 API a_melody_e2_instrument_ptr[8];
364 API d_melody_e2_deltatime;
365
366 API a_d_macc_thr_afs[8];
367 API a_d_macc_thr_ahs[6];
368 }
369 T_NDB_MCU_DSP;
370
371 typedef struct
372 {
373 API_SIGNED d_transfer_rate;
374
375 // Common GSM/GPRS
376 // These words specified the latencies to applies on some peripherics
377 API_SIGNED d_lat_mcu_bridge;
378 API_SIGNED d_lat_mcu_hom2sam;
379 API_SIGNED d_lat_mcu_bef_fast_access;
380 API_SIGNED d_lat_dsp_after_sam;
381
382 // DSP Start address
383 API_SIGNED d_gprs_install_address;
384
385 API_SIGNED d_misc_config;
386
387 API_SIGNED d_cn_sw_workaround;
388
389 API_SIGNED d_hole2_param[4];
390
391 //...................................Frequency Burst.
392 API_SIGNED d_fb_margin_beg;
393 API_SIGNED d_fb_margin_end;
394 API_SIGNED d_nsubb_idle;
395 API_SIGNED d_nsubb_dedic;
396 API_SIGNED d_fb_thr_det_iacq;
397 API_SIGNED d_fb_thr_det_track;
398 //...................................Demodulation.
399 API_SIGNED d_dc_off_thres;
400 API_SIGNED d_dummy_thres;
401 API_SIGNED d_dem_pond_gewl;
402 API_SIGNED d_dem_pond_red;
403
404 //...................................TCH Full Speech.
405 API_SIGNED d_maccthresh1;
406 API_SIGNED d_mldt;
407 API_SIGNED d_maccthresh;
408 API_SIGNED d_gu;
409 API_SIGNED d_go;
410 API_SIGNED d_attmax;
411 API_SIGNED d_sm;
412 API_SIGNED d_b;
413
414 // V42Bis module
415 API_SIGNED d_v42b_switch_hyst;
416 API_SIGNED d_v42b_switch_min;
417 API_SIGNED d_v42b_switch_max;
418 API_SIGNED d_v42b_reset_delay;
419
420 //...................................TCH Half Speech.
421 API_SIGNED d_ldT_hr;
422 API_SIGNED d_maccthresh_hr;
423 API_SIGNED d_maccthresh1_hr;
424 API_SIGNED d_gu_hr;
425 API_SIGNED d_go_hr;
426 API_SIGNED d_b_hr;
427 API_SIGNED d_sm_hr;
428 API_SIGNED d_attmax_hr;
429
430 //...................................TCH Enhanced FR Speech.
431 API_SIGNED c_mldt_efr;
432 API_SIGNED c_maccthresh_efr;
433 API_SIGNED c_maccthresh1_efr;
434 API_SIGNED c_gu_efr;
435 API_SIGNED c_go_efr;
436 API_SIGNED c_b_efr;
437 API_SIGNED c_sm_efr;
438 API_SIGNED c_attmax_efr;
439
440 //...................................CHED
441 API_SIGNED d_sd_min_thr_tchfs;
442 API_SIGNED d_ma_min_thr_tchfs;
443 API_SIGNED d_md_max_thr_tchfs;
444 API_SIGNED d_md1_max_thr_tchfs;
445
446 API_SIGNED d_sd_min_thr_tchhs;
447 API_SIGNED d_ma_min_thr_tchhs;
448 API_SIGNED d_sd_av_thr_tchhs;
449 API_SIGNED d_md_max_thr_tchhs;
450 API_SIGNED d_md1_max_thr_tchhs;
451
452 API_SIGNED d_sd_min_thr_tchefs;
453 API_SIGNED d_ma_min_thr_tchefs;
454 API_SIGNED d_md_max_thr_tchefs;
455 API_SIGNED d_md1_max_thr_tchefs;
456
457 API_SIGNED d_wed_fil_ini;
458 API_SIGNED d_wed_fil_tc;
459 API_SIGNED d_x_min;
460 API_SIGNED d_x_max;
461 API_SIGNED d_slope;
462 API_SIGNED d_y_min;
463 API_SIGNED d_y_max;
464 API_SIGNED d_wed_diff_threshold;
465 API_SIGNED d_mabfi_min_thr_tchhs;
466
467 // FACCH module
468 API_SIGNED d_facch_thr;
469
470 // IDS module
471 API_SIGNED d_max_ovsp_ul;
472 API_SIGNED d_sync_thres;
473 API_SIGNED d_idle_thres;
474 API_SIGNED d_m1_thres;
475 API_SIGNED d_max_ovsp_dl;
476 API_SIGNED d_gsm_bgd_mgt;
477
478 // FIR coefficients
479 API a_fir_holes[4];
480 API a_fir31_uplink[31];
481 API a_fir31_downlink[31];
482 }
483 T_PARAM_MCU_DSP;
484
485 typedef struct
486 {
487 API d_debug_ptr_begin;
488 API d_debug_ptr_end;
489 }
490 T_DB2_DSP_TO_MCU;