FreeCalypso > hg > freecalypso-tools
comparison target-utils/pirexplore/lcd.c @ 502:cb33d81f1386
pirexplore SPCA552E init delays changed from bogo-ms to true ms
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 27 May 2019 02:01:26 +0000 |
parents | 87cb03b35f77 |
children |
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501:7a6eba04c1bb | 502:cb33d81f1386 |
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6 #include "types.h" | 6 #include "types.h" |
7 | 7 |
8 #define GPIO_OUT_REG (*(volatile u16 *)0xFFFE4802) | 8 #define GPIO_OUT_REG (*(volatile u16 *)0xFFFE4802) |
9 #define nCS4_ADDR0 (*(volatile u16 *)0x02800000) | 9 #define nCS4_ADDR0 (*(volatile u16 *)0x02800000) |
10 #define nCS4_ADDR2 (*(volatile u16 *)0x02800002) | 10 #define nCS4_ADDR2 (*(volatile u16 *)0x02800002) |
11 | |
12 #define DELAY_1MS 13000 | |
11 | 13 |
12 fb_spca_write(addr, data) | 14 fb_spca_write(addr, data) |
13 { | 15 { |
14 GPIO_OUT_REG &= 0xFF7F; | 16 GPIO_OUT_REG &= 0xFF7F; |
15 nCS4_ADDR0 = addr; | 17 nCS4_ADDR0 = addr; |
43 * Apparently we have to give it a reset pulse, then immediately | 45 * Apparently we have to give it a reset pulse, then immediately |
44 * do the black magic register write sequence. | 46 * do the black magic register write sequence. |
45 */ | 47 */ |
46 GPIO_OUT_REG = 0x0000; | 48 GPIO_OUT_REG = 0x0000; |
47 GPIO_OUT_REG = 0x0012; | 49 GPIO_OUT_REG = 0x0012; |
48 /* non-understandable voodoo copied from OsmocomBB */ | 50 /* |
51 * The non-understandable voodoo that follows has been copied from | |
52 * OsmocomBB, and more recently has been updated to use true ms | |
53 * delays instead of bogo-ms. OBB's original code used their | |
54 * delay_ms() function, but the latter implements a delay in | |
55 * bogo-milliseconds instead of true ms, with 1 bogo-ms equal to | |
56 * 400 us in actual physical time. | |
57 */ | |
49 fb_spca_write(0x7e, 0x00); /* internal register access */ | 58 fb_spca_write(0x7e, 0x00); /* internal register access */ |
50 osmo_delay_ms(10); | 59 wait_ARM_cycles(DELAY_1MS * 4); /* 10 bogo-ms = 4 ms */ |
51 fb_spca_write(0x7a, 0x00); /* keep CPU in reset state */ | 60 fb_spca_write(0x7a, 0x00); /* keep CPU in reset state */ |
52 osmo_delay_ms(10); | 61 wait_ARM_cycles(DELAY_1MS * 4); /* 10 bogo-ms = 4 ms */ |
53 fb_spca_write(0x7f, 0x00); /* select main page */ | 62 fb_spca_write(0x7f, 0x00); /* select main page */ |
54 osmo_delay_ms(5); | 63 wait_ARM_cycles(DELAY_1MS * 2); /* 5 bogo-ms = 2 ms */ |
55 fb_spca_write(0x72, 0x07); /* don't reshape timing, 16 bit mode */ | 64 fb_spca_write(0x72, 0x07); /* don't reshape timing, 16 bit mode */ |
56 fb_spca_write(0x14, 0x03); | 65 fb_spca_write(0x14, 0x03); |
57 fb_spca_write(0x7f, 0x00); /* select main page */ | 66 fb_spca_write(0x7f, 0x00); /* select main page */ |
58 osmo_delay_ms(5); | 67 wait_ARM_cycles(DELAY_1MS * 2); /* 5 bogo-ms = 2 ms */ |
59 fb_spca_write(0x06, 0xff); | 68 fb_spca_write(0x06, 0xff); |
60 fb_spca_write(0x7f, 0x09); | 69 fb_spca_write(0x7f, 0x09); |
61 fb_spca_write(0x19, 0x08); /* backlight: 0x08 is on, 0x0c is off */ | 70 fb_spca_write(0x19, 0x08); /* backlight: 0x08 is on, 0x0c is off */ |
62 fb_spca_write(0x23, 0x18); | 71 fb_spca_write(0x23, 0x18); |
63 } | 72 } |