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comparison target-utils/flash-boot-test/uartinit.S @ 200:cc6594a7fc7a

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target-utils/flash-boot-test: added UART init, needed for mode 1
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 01 May 2017 20:02:49 +0000
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199:5515360e2f61 200:cc6594a7fc7a
1 /*
2 * The UART initialization code in this assembly module has been lifted
3 * from the disassembly of the Calypso boot ROM, and slightly adapted
4 * for our needs.
5 */
6
7 .text
8 .code 32
9 .globl uart_init
10
11 uart_init:
12 stmfd sp!, {r4-r11,lr}
13 @ prepare UART init values
14 mov r11, #3
15 mov r5, #0
16 mov r10, #7 @ baud rate divisor for 115200 baud
17 mov r9, #0x80
18 mov r7, #0xbf
19 mov r4, #7
20 @ UART base address
21 ldr r6, =uart_base
22 ldr r12, [r6]
23 add r3, r12, #8
24 @ R3 points to register 8 (MDR1)
25 @ write 07 into it: reset mode
26 strb r4, [r3]
27 add r0, r12, #3
28 @ R0 points to register 3 (LCR)
29 @ write BF into it: map in the extended registers
30 strb r7, [r0]
31 add r1, r12, #2
32 @ R1 points to register 2: EFR under current mapping
33 @ set bit 4: enable enhanced functions
34 ldrb r8, [r1]
35 orr r8, r8, #0x10
36 strb r8, [r1]
37 @ write 80 into LCR: map in the baud rate divisor registers
38 strb r9, [r0]
39 @ reg 2 (pointed to by R1) is now IIR/FCR
40 @ write 07 into FCR: FIFOs enabled and cleared, no DMA
41 strb r4, [r1]
42 @ write BF into LCR again
43 strb r7, [r0]
44 @ load baud rate divisor
45 strb r10, [r12]
46 strb r5, [r12, #1]
47 @ write 03 into LCR: restore normal registers, 8N1
48 strb r11, [r0]
49 @ write 00 into MDR1: plain UART mode
50 strb r5, [r3]
51 ldmfd sp!, {r4-r11,pc}