FreeCalypso > hg > freecalypso-tools
comparison target-utils/lunadrv/haoran.c @ 700:db9a8e88e63f
target-utils lunadrv program written, compiles
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Thu, 07 May 2020 02:19:51 +0000 |
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699:c354c261f635 | 700:db9a8e88e63f |
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1 #include "types.h" | |
2 #include "luna.h" | |
3 | |
4 /* | |
5 * ILI9225G register init for HaoRan HT020K1QC36S LCD. | |
6 */ | |
7 | |
8 init_haoran() | |
9 { | |
10 /* reset pulse */ | |
11 CNTL_RST_REG |= EXT_RESET; | |
12 wait_ARM_cycles(DELAY_1MS * 10); | |
13 CNTL_RST_REG &= ~EXT_RESET; | |
14 wait_ARM_cycles(DELAY_1MS * 50); | |
15 /* start register init */ | |
16 LCD_REG_WR(0x0001, 0x011c); // set SS and NL bit | |
17 LCD_REG_WR(0x0002, 0x0100); // set 1 line inversion | |
18 LCD_REG_WR(0x0003, 0x1030); // set GRAM write direction and BGR=1. | |
19 LCD_REG_WR(0x0008, 0x0808); // set BP and FP | |
20 LCD_REG_WR(0x000F, 0x0901); // Set frame rate | |
21 wait_ARM_cycles(DELAY_1MS * 10); | |
22 LCD_REG_WR(0x0010, 0x0000); // Set SAP,DSTB,STB | |
23 LCD_REG_WR(0x0011, 0x1B41); // Set APON,PON,AON,VCI1EN,VC | |
24 wait_ARM_cycles(DELAY_1MS * 50); | |
25 LCD_REG_WR(0x0012, 0x200E); // Internal reference voltage= Vci; | |
26 LCD_REG_WR(0x0013, 0x0052); // Set GVDD | |
27 LCD_REG_WR(0x0014, 0x4B5C); // Set VCOMH/VCOML voltage | |
28 //------------- Set GRAM area ------------------// | |
29 LCD_REG_WR(0x0030, 0x0000); | |
30 LCD_REG_WR(0x0031, 0x00DB); | |
31 LCD_REG_WR(0x0032, 0x0000); | |
32 LCD_REG_WR(0x0033, 0x0000); | |
33 LCD_REG_WR(0x0034, 0x00DB); | |
34 LCD_REG_WR(0x0035, 0x0000); | |
35 LCD_REG_WR(0x0036, 0x00AF); | |
36 LCD_REG_WR(0x0037, 0x0000); | |
37 LCD_REG_WR(0x0038, 0x00DB); | |
38 LCD_REG_WR(0x0039, 0x0000); | |
39 // ----------- Adjust the Gamma Curve ----------// | |
40 LCD_REG_WR(0x0050, 0x0000); | |
41 LCD_REG_WR(0x0051, 0x0705); | |
42 LCD_REG_WR(0x0052, 0x0C0A); | |
43 LCD_REG_WR(0x0053, 0x0401); | |
44 LCD_REG_WR(0x0054, 0x040C); | |
45 LCD_REG_WR(0x0055, 0x0608); | |
46 LCD_REG_WR(0x0056, 0x0000); | |
47 LCD_REG_WR(0x0057, 0x0104); | |
48 LCD_REG_WR(0x0058, 0x0E06); | |
49 LCD_REG_WR(0x0059, 0x060E); | |
50 wait_ARM_cycles(DELAY_1MS * 50); | |
51 LCD_REG_WR(0x0007, 0x1017); | |
52 return(0); | |
53 } |