FreeCalypso > hg > freecalypso-tools
diff target-utils/lunadrv/formike.c @ 832:21e0e6492cda
lunadrv: add init-kwh for KWH020ST23-F01 LCD
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Tue, 22 Jun 2021 02:24:38 +0000 |
parents | target-utils/lunadrv/haoran.c@db9a8e88e63f |
children |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/lunadrv/formike.c Tue Jun 22 02:24:38 2021 +0000 @@ -0,0 +1,56 @@ +#include "types.h" +#include "luna.h" + +/* + * ILI9225G register init for Formike KWH020ST23-F01 LCD. This initialization + * is almost exactly the same as for our previous HaoRan HT020K1QC36S LCD, + * except for a different VCOMH setting in register 0x14. Our Formike sales + * engineer confirmed that the new register setting is required for the new LCD. + */ + +init_formike() +{ + /* reset pulse */ + CNTL_RST_REG |= EXT_RESET; + wait_ARM_cycles(DELAY_1MS * 10); + CNTL_RST_REG &= ~EXT_RESET; + wait_ARM_cycles(DELAY_1MS * 50); + /* start register init */ + LCD_REG_WR(0x0001, 0x011c); // set SS and NL bit + LCD_REG_WR(0x0002, 0x0100); // set 1 line inversion + LCD_REG_WR(0x0003, 0x1030); // set GRAM write direction and BGR=1. + LCD_REG_WR(0x0008, 0x0808); // set BP and FP + LCD_REG_WR(0x000F, 0x0901); // Set frame rate + wait_ARM_cycles(DELAY_1MS * 10); + LCD_REG_WR(0x0010, 0x0000); // Set SAP,DSTB,STB + LCD_REG_WR(0x0011, 0x1B41); // Set APON,PON,AON,VCI1EN,VC + wait_ARM_cycles(DELAY_1MS * 50); + LCD_REG_WR(0x0012, 0x200E); // Internal reference voltage= Vci; + LCD_REG_WR(0x0013, 0x0052); // Set GVDD + LCD_REG_WR(0x0014, 0x535C); // new VCOMH setting for KWH020ST23-F01 + //------------- Set GRAM area ------------------// + LCD_REG_WR(0x0030, 0x0000); + LCD_REG_WR(0x0031, 0x00DB); + LCD_REG_WR(0x0032, 0x0000); + LCD_REG_WR(0x0033, 0x0000); + LCD_REG_WR(0x0034, 0x00DB); + LCD_REG_WR(0x0035, 0x0000); + LCD_REG_WR(0x0036, 0x00AF); + LCD_REG_WR(0x0037, 0x0000); + LCD_REG_WR(0x0038, 0x00DB); + LCD_REG_WR(0x0039, 0x0000); + // ----------- Adjust the Gamma Curve ----------// + LCD_REG_WR(0x0050, 0x0000); + LCD_REG_WR(0x0051, 0x0705); + LCD_REG_WR(0x0052, 0x0C0A); + LCD_REG_WR(0x0053, 0x0401); + LCD_REG_WR(0x0054, 0x040C); + LCD_REG_WR(0x0055, 0x0608); + LCD_REG_WR(0x0056, 0x0000); + LCD_REG_WR(0x0057, 0x0104); + LCD_REG_WR(0x0058, 0x0E06); + LCD_REG_WR(0x0059, 0x060E); + wait_ARM_cycles(DELAY_1MS * 50); + LCD_REG_WR(0x0007, 0x1017); + return(0); +}