--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/target-utils/flash-boot-test/uartinit.S	Mon May 01 20:02:49 2017 +0000
@@ -0,0 +1,51 @@
+/*
+ * The UART initialization code in this assembly module has been lifted
+ * from the disassembly of the Calypso boot ROM, and slightly adapted
+ * for our needs.
+ */
+
+	.text
+	.code	32
+	.globl	uart_init
+
+uart_init:
+	stmfd	sp!, {r4-r11,lr}
+@ prepare UART init values
+	mov	r11, #3
+	mov	r5, #0
+	mov	r10, #7		@ baud rate divisor for 115200 baud
+	mov	r9, #0x80
+	mov	r7, #0xbf
+	mov	r4, #7
+@ UART base address
+	ldr	r6, =uart_base
+	ldr	r12, [r6]
+	add	r3, r12, #8
+@ R3 points to register 8 (MDR1)
+@ write 07 into it: reset mode
+	strb	r4, [r3]
+	add	r0, r12, #3
+@ R0 points to register 3 (LCR)
+@ write BF into it: map in the extended registers
+	strb	r7, [r0]
+	add	r1, r12, #2
+@ R1 points to register 2: EFR under current mapping
+@ set bit 4: enable enhanced functions
+	ldrb	r8, [r1]
+	orr	r8, r8, #0x10
+	strb	r8, [r1]
+@ write 80 into LCR: map in the baud rate divisor registers
+	strb	r9, [r0]
+@ reg 2 (pointed to by R1) is now IIR/FCR
+@ write 07 into FCR: FIFOs enabled and cleared, no DMA
+	strb	r4, [r1]
+@ write BF into LCR again
+	strb	r7, [r0]
+@ load baud rate divisor
+	strb	r10, [r12]
+	strb	r5, [r12, #1]
+@ write 03 into LCR: restore normal registers, 8N1
+	strb	r11, [r0]
+@ write 00 into MDR1: plain UART mode
+	strb	r5, [r3]
+	ldmfd	sp!, {r4-r11,pc}