FreeCalypso > hg > freecalypso-tools
view rvinterf/include/l1tm.h @ 465:003e48f8ebe1
rvinterf/etmsync/fsnew.c: cast 0 to (char *) for execl sentinel
I generally don't use NULL and use plain 0 instead, based on a "NULL
considered harmful" discussion on the classiccmp mailing list many aeons
ago (I couldn't find it, and I reason that it must have been 2005 or
earlier), but a recent complaint by a packager sent me searching, and I
found this:
https://ewontfix.com/11/
While I don't give a @#$% about "modern" systems and code-nazi tools,
I realized that passing a plain 0 as a pointer sentinel in execl is wrong
because it will break on systems where pointers are longer than the plain
int type. Again, I don't give a @#$% about the abomination of x86_64 and
the like, but if anyone ever manages to port my code to something like a
PDP-11 (16-bit int, 32-bit long and pointers), then passing a plain 0
as a function argument where a pointer is expected most definitely won't
work: if the most natural stack slot and SP alignment unit is 16 bits,
fitting an int, with longs and pointers taking up two such slots, then
the call stack will be totally wrong with a plain 0 passed for a pointer.
Casting the 0 to (char *) ought to be the most kosher solution for the
most retro systems possible.
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 11 Feb 2019 00:00:19 +0000 |
| parents | cae9cb333c2c |
| children |
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/* * This header file contains various definitions for talking to the * L1TM firmware component. */ enum RF_PARAM { BCCH_ARFCN = 1, TCH_ARFCN = 2, MON_ARFCN = 3, PDTCH_ARFCN = 4, STD_BAND_FLAG = 7, AFC_ENA_FLAG = 8, AFC_DAC_VALUE = 9, INITIAL_AFC_DAC = 10, MULTISLOT_CLASS = 20 }; enum RF_TABLE { RX_AGC_TABLE = 8, AFC_PARAMS = 9, RX_AGC_GLOBAL_PARAMS = 12, RX_IL_2_AGC_MAX = 13, RX_IL_2_AGC_PWR = 14, RX_IL_2_AGC_AV = 15, TX_LEVELS = 16, // 16=GSM900, 32=DCS1800, 48=PCS1900 TX_CAL_CHAN = 17, // 17=GSM900, 33=DCS1800, 49=PCS1900 TX_CAL_TEMP = 20, // 20=GSM900, 36=DCS1800, 52=PCS1900 TX_CAL_EXTREME = 19, // 19=GSM900, 35=DCS1800, 51=PCS1900 RX_CAL_CHAN = 25, // 25=GSM900, 41=DCS1800, 57=PCS1900 RX_CAL_TEMP = 26, // 26=GSM900, 42=DCS1800, 58=PCS1900 RX_CAL_LEVEL = 27, // 27=GSM900, 43=DCS1800, 59=PCS1900 RX_AGC_PARAMS = 31, // 31=GSM900, 47=DCS1800, 63=PCS1900 RX_AGC_PARAMS_PCS = 63, TX_DATA_BUFFER = 80, RLC_TX_BUFFER_CS1 = 81, RLC_TX_BUFFER_CS2 = 82, RLC_TX_BUFFER_CS3 = 83, RLC_TX_BUFFER_CS4 = 84 }; enum RX_PARAM { RX_AGC_GAIN = 1, RX_TIMESLOT = 2, RX_AGC_ENA_FLAG = 8, RX_PM_ENABLE = 9, RX_FRONT_DELAY = 10, RX_FLAGS_CAL = 14, RX_FLAGS_PLATFORM = 15, RX_FLAGS_IQ_SWAP = 17, RX_FLAGS_ALL = 18, RX_GPRS_SLOTS = 28, RX_GPRS_CODING = 29 }; enum TX_PARAM { TX_PWR_LEVEL = 1, TX_APC_DAC = 4, TX_RAMP_TEMPLATE = 5, TX_CHAN_CAL_TABLE = 6, TX_RESERVED = 7, TX_BURST_TYPE = 8, TX_BURST_DATA = 9, TX_TIMING_ADVANCE = 10, TX_TRAINING_SEQ = 11, TX_PWR_SKIP = 13, TX_FLAGS_CAL = 14, TX_FLAGS_PLATFORM = 15, TX_FLAGS_IQ_SWAP = 17, TX_FLAGS_ALL = 18, TX_GPRS_POWER0 = 20, TX_GPRS_POWER1 = 21, TX_GPRS_POWER2 = 22, TX_GPRS_POWER3 = 23, TX_GPRS_POWER4 = 24, TX_GPRS_POWER5 = 25, TX_GPRS_POWER6 = 26, TX_GPRS_POWER7 = 27, TX_GPRS_SLOTS = 28, TX_GPRS_CODING = 29 }; enum MISC_PARAM { GPIOSTATE0 = 8, GPIODIR0 = 9, GPIOSTATE1 = 10, GPIODIR1 = 11, GPIOSTATE0P = 12, GPIODIR0P = 13, GPIOSTATE1P = 14, GPIODIR1P = 15, ADC_INTERVAL = 18, ADC_ENA_FLAG = 19, CONVERTED_ADC0 = 20, CONVERTED_ADC1 = 21, CONVERTED_ADC2 = 22, CONVERTED_ADC3 = 23, CONVERTED_ADC4 = 24, CONVERTED_ADC5 = 25, CONVERTED_ADC6 = 26, CONVERTED_ADC7 = 27, CONVERTED_ADC8 = 28, RAW_ADC0 = 30, RAW_ADC1 = 31, RAW_ADC2 = 32, RAW_ADC3 = 33, RAW_ADC4 = 34, RAW_ADC5 = 35, RAW_ADC6 = 36, RAW_ADC7 = 37, RAW_ADC8 = 38, ADC0_COEFF_A = 50, ADC1_COEFF_A = 51, ADC2_COEFF_A = 52, ADC3_COEFF_A = 53, ADC4_COEFF_A = 54, ADC5_COEFF_A = 55, ADC6_COEFF_A = 56, ADC7_COEFF_A = 57, ADC8_COEFF_A = 58, ADC0_COEFF_B = 60, ADC1_COEFF_B = 61, ADC2_COEFF_B = 62, ADC3_COEFF_B = 63, ADC4_COEFF_B = 64, ADC5_COEFF_B = 65, ADC6_COEFF_B = 66, ADC7_COEFF_B = 67, ADC8_COEFF_B = 68, SLEEP_MODE = 80, CURRENT_TM_MODE = 127 }; enum STATS_CONFIG { LOOPS = 16, AUTO_RESULT_LOOPS = 17, AUTO_RESET_LOOPS = 18, STAT_GPRS_SLOTS = 20, STAT_TYPE = 24, STAT_BITMASK = 25 }; enum STATS_READ { ACCUMULATED_RX_STATS = 1, MOST_RECENT_RX_STATS = 2 }; enum BITMASK { RSSI = 0x0001, DSP_PM = 0x0002, ANGLE_MEAN = 0x0004, ANGLE_VAR = 0x0008, SNR_MEAN = 0x0010, SNR_VAR = 0x0020, TOA_MEAN = 0x0040, TOA_VAR = 0x0080, RESERVED1 = 0x0100, RESERVED2 = 0x0200, ANGLE_MIN = 0x0400, ANGLE_MAX = 0x0800, FRAME_NUMBER = 0x1000, RUNS = 0x2000, SUCCESSES = 0x4000, BSIC = 0x8000 }; enum RF_ENABLE_E { STOP_ALL = 0, RX_TCH = 1, TX_TCH = 2, RX_TX_TCH = 3, RX_TX_PDTCH = 4, RX_TCH_CONT = 8, TX_TCH_CONT = 9, BCCH_LOOP = 10, SB_LOOP = 11, FB1_LOOP = 12, FB0_LOOP = 13, SINGLE_PM = 15, RX_TX_PDTCH_MON = 16, RX_TX_MON_TCH = 19, RX_TX_MON = 27 }; enum ME_CFG_WRITE_E { CFG_WRITE_MKDIRS = 100, CFG_WRITE_RF_CAL = 102, CFG_WRITE_RF_CFG = 103, CFG_WRITE_TX_CAL = 104, CFG_WRITE_TX_CFG = 105, CFG_WRITE_RX_CAL = 106, CFG_WRITE_RX_CFG = 107, CFG_WRITE_SYS_CAL = 108, CFG_WRITE_SYS_CFG = 109 }; #define MAX_RF_TABLE_SIZE 128