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PL-J flash PPB ops: rework for full verification of lock state
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 02 Dec 2023 08:22:00 +0000
parents 26bb2c069427
children
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# This loadtool init script provides memory interface register setup
# for targets which fit the following criteria:
#
# Classic chip select arrangement: nCS0 for flash and nCS1 for XRAM
# 4 wait states are to be used (register setting 00A4)
# No ADD22 - both flash and XRAM are 4 MiB or less

w16 fffffb00 00A4
w16 fffffb02 00A4