FreeCalypso > hg > freecalypso-tools
view target-utils/simtest/setup.c @ 928:65953c172f24
rvinterf/lowlevel: new hex dump format
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 23 May 2023 05:23:19 +0000 |
parents | 06ad5e30e8d0 |
children |
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#include "types.h" #include "abbdefs.h" #include "simregs.h" #define WAIT_ONE_TDMA 60000 extern u16 abb_reg_read(); extern void abb_reg_write(); u16 conf1_reg; void cmd_setup(argbulk) char *argbulk; { u16 abb_sim_reg; abb_sim_reg = abb_reg_read(VRPCSIM); if (!(abb_sim_reg & 2)) { printf("ERROR: VRSIM is not enabled\n"); return; } if (!(abb_sim_reg & 4)) { printf("ERROR: VRSIM is not in proper regulation\n"); return; } /* TI's SIM_ManualStart() code follows */ SIMREGS.conf1 = conf1_reg = 0x8004; SIMREGS.cmd = SIM_CMD_CLKEN; SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_STOP; wait_ARM_cycles(WAIT_ONE_TDMA * 4); SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_SWRST; wait_ARM_cycles(WAIT_ONE_TDMA); SIMREGS.conf2 = 0x0940; //enter in manual mode to start the ATR sequence SIMREGS.conf1 = conf1_reg |= SIM_CONF1_BYPASS; wait_ARM_cycles(WAIT_ONE_TDMA); SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SVCCLEV; wait_ARM_cycles(WAIT_ONE_TDMA); abb_sim_reg |= 8; abb_reg_write(VRPCSIM, abb_sim_reg); wait_ARM_cycles(WAIT_ONE_TDMA); SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_SIOLOW; wait_ARM_cycles(WAIT_ONE_TDMA); SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SCLKEN; SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_TXRX; //set to receive mode }