view target-utils/flash-boot-test/uartinit.S @ 995:74024eb17e04

fc-loadtool help: improve language regarding 16 MiB flash chips In FC project history, 16 MiB flash originally meant Pirelli DP-L10. Then we got FCDEV3B with the same flash (our own design), but now we are discovering more Calypso devices that used such large flash, both late Calypso era (Sony Ericsson K2x0) as well as much earlier ones (FIC FLUID devices.txt file with 2004 dates, Leonardo+ rev 5). Hence we need to migrate to more generic or neutral language in associated documentation, without giving elevated status to specific examples that drove our early project history.
author Mychaela Falconia <falcon@freecalypso.org>
date Sun, 03 Dec 2023 21:11:12 +0000
parents cc6594a7fc7a
children
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/*
 * The UART initialization code in this assembly module has been lifted
 * from the disassembly of the Calypso boot ROM, and slightly adapted
 * for our needs.
 */

	.text
	.code	32
	.globl	uart_init

uart_init:
	stmfd	sp!, {r4-r11,lr}
@ prepare UART init values
	mov	r11, #3
	mov	r5, #0
	mov	r10, #7		@ baud rate divisor for 115200 baud
	mov	r9, #0x80
	mov	r7, #0xbf
	mov	r4, #7
@ UART base address
	ldr	r6, =uart_base
	ldr	r12, [r6]
	add	r3, r12, #8
@ R3 points to register 8 (MDR1)
@ write 07 into it: reset mode
	strb	r4, [r3]
	add	r0, r12, #3
@ R0 points to register 3 (LCR)
@ write BF into it: map in the extended registers
	strb	r7, [r0]
	add	r1, r12, #2
@ R1 points to register 2: EFR under current mapping
@ set bit 4: enable enhanced functions
	ldrb	r8, [r1]
	orr	r8, r8, #0x10
	strb	r8, [r1]
@ write 80 into LCR: map in the baud rate divisor registers
	strb	r9, [r0]
@ reg 2 (pointed to by R1) is now IIR/FCR
@ write 07 into FCR: FIFOs enabled and cleared, no DMA
	strb	r4, [r1]
@ write BF into LCR again
	strb	r7, [r0]
@ load baud rate divisor
	strb	r10, [r12]
	strb	r5, [r12, #1]
@ write 03 into LCR: restore normal registers, 8N1
	strb	r11, [r0]
@ write 00 into MDR1: plain UART mode
	strb	r5, [r3]
	ldmfd	sp!, {r4-r11,pc}