FreeCalypso > hg > freecalypso-tools
view target-utils/calversion/dsp_const.h @ 497:74610c4f10f7
target-utils: added 10 ms delay at the end of abb_power_off()
The deosmification of the ABB access code (replacement of osmo_delay_ms()
bogus delays with correctly-timed ones, which are significantly shorter)
had one annoying side effect: when executing the poweroff command from
any of the programs, one last '=' prompt character was being sent (and
received by the x86 host) as the Calypso board powers off. With delays
being shorter now, the abb_power_off() function was returning and the
standalone program's main loop was printing its prompt before the Iota chip
fully executed the switch-off sequence!
I thought about inserting an endless tight loop at the end of the
abb_power_off() function, but the implemented solution of a 10 ms delay
is a little nicer IMO because if the DEVOFF operation doesn't happen for
some reason in a manual hacking scenario, there won't be an artificial
blocker in the form of a tight loop keeping us from further poking around.
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sat, 25 May 2019 20:44:05 +0000 |
parents | 1dcc9e4b71fd |
children |
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/* * This header file is a subset of l1_const.h from TCS211, defining * those constants which are needed for the DSP bring-up code in * the dsp_bringup.c module. */ #define NO_PAR 0 #define NO_TASK 0 #define ALL_TASK 0xffffffff #define ALL_PARAM 0xffffffff #define TRUE 1 #define TRUE_L 1L #define FALSE 0 #define NOT_PENDING 0 #define PENDING 1 #define INACTIVE 2 #define ACTIVE 3 #define RE_ENTERED 4 #define WAIT_IQ 5 //--------------------------------------------- // MCU-DSP bit-field bit position definitions //--------------------------------------------- #define GPRS_SCHEDULER 1 // Select GPRS scheduler #define GSM_SCHEDULER 2 // Select GSM scheduler // DSP state need to be used to enter Deep Sleep mode #define C_DSP_IDLE3 3 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800))) // **************************************************************** // PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS // **************************************************************** #define C_POND_RED 1L #define D_NSUBB_IDLE 296L #define D_NSUBB_DEDIC 30L #define D_FB_THR_DET_IACQ 0x3333L #define D_FB_THR_DET_TRACK 0x28f6L #define D_DC_OFF_THRES 0x7fffL #define D_DUMMY_THRES 17408L #define D_DEM_POND_GEWL 26624L #define D_DEM_POND_RED 20152L #define D_HOLE 0L #define D_TRANSFER_RATE 0x6666L // Full Rate vocoder definitions. #define D_MACCTHRESH1 7872L #define D_MLDT -4L #define D_MACCTHRESH 7872L #define D_GU 5772L #define D_GO 7872L #define D_ATTMAX 53L #define D_SM -892L #define D_B 208L #define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED) #define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED) #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED) #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED) // Frequency burst definitions #define D_FB_MARGIN_BEG 24 #define D_FB_MARGIN_END 22 // V42bis definitions #define D_V42B_SWITCH_HYST 16L #define D_V42B_SWITCH_MIN 64L #define D_V42B_SWITCH_MAX 250L #define D_V42B_RESET_DELAY 10L #define D_LAT_MCU_BRIDGE 0x000FL #define D_LAT_MCU_HOM2SAM 0x000CL #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L #define D_LAT_DSP_AFTER_SAM 0x0004L // Background Task in GSM mode: Initialization. #define D_GSM_BGD_MGT 0L #define D_MISC_CONFIG 1L // Half Rate vocoder and ched definitions. #define D_SD_MIN_THR_TCHHS 37L #define D_MA_MIN_THR_TCHHS 344L #define D_MD_MAX_THR_TCHHS 2175L #define D_MD1_MAX_THR_TCHHS 138L #define D_SD_AV_THR_TCHHS 1845L #define D_WED_FIL_TC 0x7c00L #define D_WED_FIL_INI 4650L #define D_X_MIN 15L #define D_X_MAX 23L #define D_Y_MIN 703L #define D_Y_MAX 2460L #define D_SLOPE 135L #define D_WED_DIFF_THRESHOLD 406L #define D_MABFI_MIN_THR_TCHHS 5320L #define D_LDT_HR -5 #define D_MACCTRESH_HR 6500 #define D_MACCTRESH1_HR 6500 #define D_GU_HR 2620 #define D_GO_HR 3700 #define D_B_HR 182 #define D_SM_HR -1608 #define D_ATTMAX_HR 53 // Enhanced Full Rate vocoder and ched definitions. #define C_MLDT_EFR -4 #define C_MACCTHRESH_EFR 8000 #define C_MACCTHRESH1_EFR 8000 #define C_GU_EFR 4522 #define C_GO_EFR 6500 #define C_B_EFR 174 #define C_SM_EFR -878 #define C_ATTMAX_EFR 53 #define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED) #define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED) #define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED) #define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED) // Integrated Data Services definitions. #define D_MAX_OVSPD_UL 8 // Detect frames containing 90% of 1s as synchro frames #define D_SYNC_THRES 0x3f50 // IDLE frames are only frames with 100 % of 1s #define D_IDLE_THRES 0x4000 #define D_M1_THRES 5 #define D_MAX_OVSP_DL 8 #define D_FACCH_THR 0 #define D_DSP_TEST 0 #define D_VERSION_NUMBER 0 #define D_TI_VERSION 0 // DSP ADRESSES //-------------------- #define DB_SIZE (4*20L) // 4 pages of 20 words... #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long #define NDB_ADR 0xFFD001A8L // NDB start address : 268 words #define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words #define DB2_R_PAGE_0 0xFFD00184L #define DB2_R_PAGE_1 0xFFD00188L