/*
 * This header file contains various definitions for talking to the old
 * non-enhanced Test Mode firmware component.
 */

/* CID opcodes */
enum 
{
  TM_INIT                    = 0x20,
  TM_MODE_SET                = 0x21,
  VERSION_GET                = 0x22,
  RF_ENABLE                  = 0x23,
  STATS_READ                 = 0x24,
  STATS_CONFIG_WRITE         = 0x25,
  STATS_CONFIG_READ          = 0x26,
  RF_PARAM_WRITE             = 0x30,
  RF_PARAM_READ              = 0x31,
  RF_TABLE_WRITE             = 0x32,
  RF_TABLE_READ              = 0x33,
  RX_PARAM_WRITE             = 0x34,
  RX_PARAM_READ              = 0x35,
  TX_PARAM_WRITE             = 0x36,
  TX_PARAM_READ              = 0x37,
  TX_TEMPLATE_WRITE          = 0x38,
  TX_TEMPLATE_READ           = 0x39,
  MEM_WRITE                  = 0x40,
  MEM_READ                   = 0x41,
  CODEC_WRITE                = 0x42,
  CODEC_READ                 = 0x43,
  MISC_PARAM_WRITE           = 0x44,
  MISC_PARAM_READ            = 0x45,
  MISC_TABLE_WRITE           = 0x46,
  MISC_TABLE_READ            = 0x47,
  MISC_ENABLE                = 0x48,
  SPECIAL_PARAM_WRITE        = 0x50,
  SPECIAL_PARAM_READ         = 0x51,
  SPECIAL_TABLE_WRITE        = 0x52,
  SPECIAL_TABLE_READ         = 0x53,
  SPECIAL_ENABLE             = 0x54,

  TPU_TABLE_WRITE            = 0x55,
  TPU_TABLE_READ             = 0x56,

  TM_FFS                     = 0x70
};

#define	TM3_MEMREAD_MAX	0x7C