view target-utils/libbase/waitarm.S @ 900:8171c5c0d804

rvinterf tree: definitions for new version of TCH tap feature
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 13 Dec 2022 03:01:41 +0000
parents 06ad5e30e8d0
children
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/*
 * This assembly module provides a wait_ARM_cycles() function similar to
 * the one in TI's firmware; it is meant to gradually replace and phase out
 * osmo_delay_ms().  One loop count for this function equals 4 ARM clock
 * cycles when running out of IRAM; if the ARM clock is 52 MHz, 13 loop counts
 * equal one microsecond.
 *
 * Note the instruction sequence difference from TI's firmware version:
 * we use the SUBS instruction (equivalent of plain SUB in Thumb) and omit
 * the CMP, which is why our version is 4 cycles per loop (when running
 * out of IRAM), as opposed to 5 cycles per loop (plus wait states as they
 * execute from flash) in TI's fw version.
 */

	.text
	.code	32
	.globl	wait_ARM_cycles
wait_ARM_cycles:
	cmp	r0, #0
	bxeq	lr
1:	subs	r0, r0, #1
	bne	1b
	bx	lr