FreeCalypso > hg > freecalypso-tools
view loadtools/scripts/dsample.config @ 338:97a72ec0a6c1
uptools/Makefile created
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 04 Feb 2018 06:05:04 +0000 |
parents | 2b5ed962c2f9 |
children | 49ee210fc4fb |
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# The following parameters go into the <p command sent to the boot ROM # The values to be used have been gleaned from the 20020917 fw image # CLKTCXO input is 13 MHz on the D-Sample, and with Calypso C05 # the max allowed PLL'ed clock is 78 MHz for the DSP and 39 MHz for the ARM. # TI's firmware sets the PLL up to multiply by 6 (giving 78 MHz) with # divide by 2 for the ARM, but the boot ROM doesn't do the latter when # the input clock is 13 MHz. Hence we'll program the PLL to multiply # by 3, putting everything at 39 MHz. pll-config 3/1 rhea-cntl 0x00 # set by 20020917 fw, hence presumed correct # The remaining settings are carried out via loadagent commands init-script cs2-4ws-8mb.init # 8 MiB flash, accessible at 0x03000000 without Compal-like problems, # but the 28F640W30B flash chip has partition quirks, so we need to # tell fc-loadtool about it explicitly instead of using CFI. flash 28f640w30b 0x03000000 # Perform a Iota poweroff when we are done exit-mode iota-off