/* Driver for uWire Master Controller inside TI Calypso */
/* lifted from OsmocomBB and ported to FreeCalypso target-utils environment */

/* (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
 *
 * All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 */

#include "types.h"

struct uwire_regs {
	u16	reg_data;
	u16	reg_csr;
	u16	reg_sr1;
	u16	reg_sr2;
	u16	reg_sr3;
};

#define	UWIRE_REGS	(*(volatile struct uwire_regs *) 0xFFFE4000)

#define UWIRE_CSR_BITS_RD(n)	(((n) & 0x1f) << 0)
#define UWIRE_CSR_BITS_WR(n)	(((n) & 0x1f) << 5)
#define UWIRE_CSR_IDX(n)	(((n) & 3) << 10)
#define UWIRE_CSR_CS_CMD	(1 << 12)
#define UWIRE_CSR_START		(1 << 13)
#define UWIRE_CSR_CSRB		(1 << 14)
#define UWIRE_CSR_RDRB		(1 << 15)

#define UWIRE_CSn_EDGE_RD	(1 << 0)	/* 1=falling 0=rising */
#define UWIRE_CSn_EDGE_WR	(1 << 1)	/* 1=falling 0=rising */
#define UWIRE_CSn_CS_LVL	(1 << 2)
#define UWIRE_CSn_FRQ_DIV2	(0 << 3)
#define UWIRE_CSn_FRQ_DIV4	(1 << 3)
#define UWIRE_CSn_FRQ_DIV8	(2 << 3)
#define UWIRE_CSn_CKH

#define UWIRE_CSn_SHIFT(n)	(((n) & 1) ? 6 : 0)
#define UWIRE_CSn_REG(n)	(((n) & 2) ? REG_SR2 : REG_SR1)

#define UWIRE_SR3_CLK_EN	(1 << 0)
#define UWIRE_SR3_CLK_DIV2	(0 << 1)
#define UWIRE_SR3_CLK_DIV4	(1 << 1)
#define UWIRE_SR3_CLK_DIV7	(2 << 1)
#define UWIRE_SR3_CLK_DIV10	(3 << 1)

static inline void _uwire_wait(int mask, int val)
{
	while ((UWIRE_REGS.reg_csr & mask) != val);
}

/*
 * Let's try changing the chip select logic from OsmocomBB way
 * to the way seen in TI's R2D source.
 */

void uwire_init(void)
{
	UWIRE_REGS.reg_sr3 = UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2;
	UWIRE_REGS.reg_sr1 = UWIRE_CSn_FRQ_DIV2;
#if 0
	UWIRE_REGS.reg_sr1 = UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2;
	UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
	_uwire_wait(UWIRE_CSR_CSRB, 0);
#endif
}

send_via_uwire(word)
	unsigned word;
{
#if 0
	/* select the chip */
	UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
	_uwire_wait(UWIRE_CSR_CSRB, 0);
#endif

	UWIRE_REGS.reg_data = word << 7;
	UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START
				| UWIRE_CSR_CS_CMD;
	_uwire_wait(UWIRE_CSR_CSRB, 0);

	/* unselect the chip */
	UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | 0;
#if 0
	_uwire_wait(UWIRE_CSR_CSRB, 0);
#endif

	return 0;
}