FreeCalypso > hg > freecalypso-tools
changeset 495:06ad5e30e8d0
target-utils: wait_ARM_cycles() changed to 4 cycles per loop
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Sat, 25 May 2019 18:51:19 +0000 |
| parents | 547c540448e5 |
| children | 3d73d4d3527f |
| files | target-utils/libbase/waitarm.S target-utils/simtest/setup.c |
| diffstat | 2 files changed, 13 insertions(+), 7 deletions(-) [+] |
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--- a/target-utils/libbase/waitarm.S Fri May 24 06:44:59 2019 +0000 +++ b/target-utils/libbase/waitarm.S Sat May 25 18:51:19 2019 +0000 @@ -1,8 +1,15 @@ /* - * This assembly module provides a wait_ARM_cycles() function just like - * in TI's firmware; it is meant to gradually replace and phase out - * osmo_delay_ms(). One loop count for this function equals 5 ARM clock - * cycles when running out of IRAM. + * This assembly module provides a wait_ARM_cycles() function similar to + * the one in TI's firmware; it is meant to gradually replace and phase out + * osmo_delay_ms(). One loop count for this function equals 4 ARM clock + * cycles when running out of IRAM; if the ARM clock is 52 MHz, 13 loop counts + * equal one microsecond. + * + * Note the instruction sequence difference from TI's firmware version: + * we use the SUBS instruction (equivalent of plain SUB in Thumb) and omit + * the CMP, which is why our version is 4 cycles per loop (when running + * out of IRAM), as opposed to 5 cycles per loop (plus wait states as they + * execute from flash) in TI's fw version. */ .text @@ -11,7 +18,6 @@ wait_ARM_cycles: cmp r0, #0 bxeq lr -1: sub r0, r0, #1 - cmp r0, #0 +1: subs r0, r0, #1 bne 1b bx lr
--- a/target-utils/simtest/setup.c Fri May 24 06:44:59 2019 +0000 +++ b/target-utils/simtest/setup.c Sat May 25 18:51:19 2019 +0000 @@ -2,7 +2,7 @@ #include "abbdefs.h" #include "simregs.h" -#define WAIT_ONE_TDMA 48000 +#define WAIT_ONE_TDMA 60000 extern u16 abb_reg_read(); extern void abb_reg_write();