FreeCalypso > hg > freecalypso-tools
changeset 441:1dcc9e4b71fd
target-utils/calversion: program written, compiles
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Wed, 26 Dec 2018 06:40:02 +0000 |
| parents | 44f73d56b6f5 |
| children | ba4171b2f980 |
| files | target-utils/calversion/Makefile target-utils/calversion/cmdtab.c target-utils/calversion/crt0.S target-utils/calversion/dsp_bringup.c target-utils/calversion/dsp_const.h target-utils/calversion/dsp_defty.h target-utils/calversion/leadapi.h target-utils/calversion/main.c target-utils/calversion/mygetchar.c |
| diffstat | 9 files changed, 992 insertions(+), 0 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/Makefile Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,29 @@ +CC= arm-elf-gcc +CFLAGS= -Os -fno-builtin +CPPFLAGS=-I../include +LD= arm-elf-ld +OBJCOPY=arm-elf-objcopy + +PROG= calversion +OBJS= crt0.o cmdtab.o dsp_bringup.o main.o mygetchar.o +LIBS= ../libcommon/libcommon.a ../libprintf/libprintf.a ../libbase/libbase.a \ + ../libc/libc.a +LIBGCC= `${CC} -print-file-name=libgcc.a` +LDS= ../env/iram.lds + +all: ${PROG}.srec + +crt0.S: ../env/crt0.S + ln -s $< . + +${PROG}.elf: ${OBJS} ${LIBS} ${LDS} + ${LD} -N --defsym Base_addr=0x800750 --defsym stack_bottom=0x83FFFC \ + -T ${LDS} -o $@ ${OBJS} ${LIBS} ${LIBGCC} + +${PROG}.srec: ${PROG}.elf + ${OBJCOPY} -O srec --srec-forceS3 --srec-len=30 $< $@ + +clean: + rm -f *.o *errs *core *.elf *.bin *.srec crt0.S + +FRC:
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/cmdtab.c Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,32 @@ +#include "cmdtab.h" + +extern void cmd_abbr(); +extern void cmd_abbw(); +extern void cmd_jump(); +extern void cmd_r8(); +extern void cmd_r16(); +extern void cmd_r32(); +extern void cmd_w8(); +extern void cmd_w16(); +extern void cmd_w32(); + +extern void cmd_memdump_human(); + +extern void abb_init(); +extern void abb_power_off(); + +const struct cmdtab cmdtab[] = { + {"abbinit", abb_init}, + {"abbr", cmd_abbr}, + {"abbw", cmd_abbw}, + {"dump", cmd_memdump_human}, + {"jump", cmd_jump}, + {"poweroff", abb_power_off}, + {"r8", cmd_r8}, + {"r16", cmd_r16}, + {"r32", cmd_r32}, + {"w8", cmd_w8}, + {"w16", cmd_w16}, + {"w32", cmd_w32}, + {0, 0} +};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/crt0.S Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,1 @@ +../env/crt0.S \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/dsp_bringup.c Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,222 @@ +/* + * This module contains the dsp_power_on() function from TCS211, + * stripped and adapted for the present DSP version determination + * standalone program. + */ + +#include "types.h" +#include "leadapi.h" +#include "dsp_const.h" +#include "dsp_defty.h" + +/* definitions originally in l1_types.h */ + +typedef unsigned char BOOL; +typedef char CHAR; + +typedef unsigned char UWORD8; +typedef signed char WORD8; + +typedef unsigned short UWORD16; +typedef short WORD16; + +typedef unsigned long UWORD32; +typedef long WORD32; + +/* definitions originally in l1_confg.h */ + +#define DSP_START 0x7000 +#define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer + +#define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips + +#define C_DSP_SW_WORK_AROUND 0x000E + +#define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after. +#define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer. +#define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst. + +/* DSP reset control register definitions */ + +#define MEM_CLKM_ADDR 0xfffffd00 /* CLKM registers addr. */ +#define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */ + +#define CLKM_LEAD_RST 0x0002 +#define CLKM_EXT_RST 0x0004 + +/*-------------------------------------------------------*/ +/* dsp_power_on() */ +/*-------------------------------------------------------*/ +/* Parameters : */ +/* Return : */ +/* Functionality : */ +/* Remarq : USART Buffer is 256 characters. While USART*/ +/* is not run during Application_Initialize */ +/* (hisrs not served because Nucleus scheduler*/ +/* is not running yet) : */ +/* ==> check string size < 256 !!!!!! */ +/*-------------------------------------------------------*/ +void dsp_power_on(void) +{ + UWORD16 dsp_start_address; + UWORD16 param_size; + + API i; + volatile API *pt; + WORD16 j; + + volatile T_NDB_MCU_DSP * dsp_ndb_ptr; + + static API_SIGNED param_tab[] = { + + D_TRANSFER_RATE, + + // ..................Latencies + D_LAT_MCU_BRIDGE, D_LAT_MCU_HOM2SAM, + + D_LAT_MCU_BEF_FAST_ACCESS, D_LAT_DSP_AFTER_SAM, + + //...................p_gprs_install_adress + D_HOLE, + + //...................d_misc_config + D_MISC_CONFIG, + + //...................d_cn_sw_workaround + C_DSP_SW_WORK_AROUND, + + //...................Reserved + D_HOLE, D_HOLE, + D_HOLE, D_HOLE, + + //...................Frequency burst + D_FB_MARGIN_BEG, D_FB_MARGIN_END, + D_NSUBB_IDLE, D_NSUBB_DEDIC, D_FB_THR_DET_IACQ, + D_FB_THR_DET_TRACK, + //...................Demodulation + D_DC_OFF_THRES, D_DUMMY_THRES, D_DEM_POND_GEWL, + D_DEM_POND_RED, + //...................TCH Full Speech + D_MACCTHRESH1, D_MLDT, D_MACCTHRESH, + D_GU, D_GO, D_ATTMAX, + D_SM, D_B, + + //...................V42 bis + D_V42B_SWITCH_HYST, D_V42B_SWITCH_MIN, D_V42B_SWITCH_MAX, + D_V42B_RESET_DELAY, + + //...................TCH Half Speech + D_LDT_HR, D_MACCTRESH_HR, D_MACCTRESH1_HR, + D_GU_HR, D_GO_HR, D_B_HR, + D_SM_HR, D_ATTMAX_HR, + + //...................Added variables for EFR + C_MLDT_EFR, C_MACCTHRESH_EFR, C_MACCTHRESH1_EFR, + C_GU_EFR, C_GO_EFR, C_B_EFR, + C_SM_EFR, C_ATTMAX_EFR, + + //...................Full rate variables + D_SD_MIN_THR_TCHFS, + D_MA_MIN_THR_TCHFS, D_MD_MAX_THR_TCHFS, D_MD1_MAX_THR_TCHFS, + + //...................TCH Half Speech + D_SD_MIN_THR_TCHHS, D_MA_MIN_THR_TCHHS, D_SD_AV_THR_TCHHS, + D_MD_MAX_THR_TCHHS, D_MD1_MAX_THR_TCHHS, + + //...................TCH Enhanced Full Rate Speech + D_SD_MIN_THR_TCHEFS, D_MA_MIN_THR_TCHEFS, D_MD_MAX_THR_TCHEFS, + D_MD1_MAX_THR_TCHEFS, D_WED_FIL_INI, + + D_WED_FIL_TC, D_X_MIN, D_X_MAX, + D_SLOPE, D_Y_MIN, D_Y_MAX, + D_WED_DIFF_THRESHOLD,D_MABFI_MIN_THR_TCHHS,D_FACCH_THR, + + D_MAX_OVSPD_UL, D_SYNC_THRES, D_IDLE_THRES, + D_M1_THRES, D_MAX_OVSP_DL, D_GSM_BGD_MGT + }; + param_size = 79; + + // NDB pointer. + dsp_ndb_ptr = (volatile T_NDB_MCU_DSP *) NDB_ADR; + + //------------- + // DSP STARTUP + //------------- + { + // Release Lead reset before DSP code/patch download to insure proper reset of DSP + printf("Releasing DSP core from reset\n"); + (*(unsigned short *) CLKM_CNTL_RST) &= ~CLKM_LEAD_RST; + + // GSM 1.5 + //----------------------------------------------------------------- + // After RESET release, DSP is in SAM Mode ! while API_CNTR (0xF900) + // register is in reset state: HOM mode, PLL off, Bridge off. No ws + // are applied for MCU<-->API access !!!!! So, MCU must wait for + // end of Leadboot execution before accessing API. + //wait_ARM_cycles(convert_nanosec_to_cycles(10000)); // wait 10us + osmo_delay_ms(10); + + // NO DOWNLOAD... + { + // Wait for READY status from DSP. + printf("Waiting for DSP bootloader READY status\n"); + while(*((volatile UWORD16 *)DOWNLOAD_STATUS) != LEAD_READY); + + // Set DSP start address. + dsp_start_address = DSP_START; + } + } + + //-------------------------------------------------------------- + // Loading of NDB parameters....... + //-------------------------------------------------------------- + printf("Loading NDB parameters\n"); + // Initialize background control variable to No background. Background tasks can be launch in GPRS + // as in GSM. + dsp_ndb_ptr->d_background_enable = 0; + dsp_ndb_ptr->d_background_abort = 0; + dsp_ndb_ptr->d_background_state = 0; + dsp_ndb_ptr->d_debug_ptr = 0x0074; + dsp_ndb_ptr->d_debug_bk = 0x0001; + dsp_ndb_ptr->d_pll_config = C_PLL_CONFIG; + dsp_ndb_ptr->p_debug_buffer = C_DEBUG_BUFFER_ADD; + dsp_ndb_ptr->d_debug_buffer_size = C_DEBUG_BUFFER_SIZE; + dsp_ndb_ptr->d_debug_trace_type = C_DEBUG_TRACE_TYPE; + + // Deep Sleep work around used on Calypso + // This init is used to backward compatibility with old patch. + dsp_ndb_ptr->d_dsp_state = C_DSP_IDLE3; + + dsp_ndb_ptr->d_audio_gain_ul = 0; + dsp_ndb_ptr->d_audio_gain_dl = 0; + + // for patch >= 2100, use new AEC + dsp_ndb_ptr->d_es_level_api = 0x5213; + dsp_ndb_ptr->d_mu_api = 0x5000; + + //-------------------------------------------------------------- + // Loading of PARAM area....... + //-------------------------------------------------------------- + printf("Loading PARAM area\n"); + // Load PARAM memory... + pt = (volatile API *) PARAM_ADR; + + for (i=0; i<param_size; i++) *pt++ = param_tab[i]; + + { + T_PARAM_MCU_DSP *pt_param = (T_PARAM_MCU_DSP *) PARAM_ADR; + + // "d_gprs_install_address" has to be set only if no PATCH is download, i.e. + // "d_gprs_install_address" is automatically set by DSP if a PATCH is download + pt_param->d_gprs_install_address = INSTALL_ADD; + } + + printf("Booting DSP main code\n"); + *(volatile UWORD16 *) DOWNLOAD_SIZE = 0; // Size=0 to force DSP to start from address... + *(volatile UWORD16 *) DOWNLOAD_ADDR = dsp_start_address; // Start address. + *(volatile UWORD16 *) DOWNLOAD_STATUS = BLOCK_READY; // Start DSP... + + osmo_delay_ms(50); + printf("DSP reports version 0x%04X 0x%04X\n", + dsp_ndb_ptr->d_version_number1, dsp_ndb_ptr->d_version_number2); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/dsp_const.h Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,154 @@ +/* + * This header file is a subset of l1_const.h from TCS211, defining + * those constants which are needed for the DSP bring-up code in + * the dsp_bringup.c module. + */ + +#define NO_PAR 0 + +#define NO_TASK 0 +#define ALL_TASK 0xffffffff +#define ALL_PARAM 0xffffffff + +#define TRUE 1 +#define TRUE_L 1L +#define FALSE 0 + +#define NOT_PENDING 0 +#define PENDING 1 + +#define INACTIVE 2 +#define ACTIVE 3 +#define RE_ENTERED 4 +#define WAIT_IQ 5 + +//--------------------------------------------- +// MCU-DSP bit-field bit position definitions +//--------------------------------------------- +#define GPRS_SCHEDULER 1 // Select GPRS scheduler +#define GSM_SCHEDULER 2 // Select GSM scheduler + +// DSP state need to be used to enter Deep Sleep mode +#define C_DSP_IDLE3 3 + +#define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800))) + +// **************************************************************** +// PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS +// **************************************************************** +#define C_POND_RED 1L +#define D_NSUBB_IDLE 296L +#define D_NSUBB_DEDIC 30L +#define D_FB_THR_DET_IACQ 0x3333L +#define D_FB_THR_DET_TRACK 0x28f6L +#define D_DC_OFF_THRES 0x7fffL +#define D_DUMMY_THRES 17408L +#define D_DEM_POND_GEWL 26624L +#define D_DEM_POND_RED 20152L +#define D_HOLE 0L +#define D_TRANSFER_RATE 0x6666L + +// Full Rate vocoder definitions. +#define D_MACCTHRESH1 7872L +#define D_MLDT -4L +#define D_MACCTHRESH 7872L +#define D_GU 5772L +#define D_GO 7872L +#define D_ATTMAX 53L +#define D_SM -892L +#define D_B 208L +#define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED) +#define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED) +#define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED) +#define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED) + +// Frequency burst definitions +#define D_FB_MARGIN_BEG 24 +#define D_FB_MARGIN_END 22 + +// V42bis definitions +#define D_V42B_SWITCH_HYST 16L +#define D_V42B_SWITCH_MIN 64L +#define D_V42B_SWITCH_MAX 250L +#define D_V42B_RESET_DELAY 10L + +#define D_LAT_MCU_BRIDGE 0x000FL + +#define D_LAT_MCU_HOM2SAM 0x000CL + +#define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L +#define D_LAT_DSP_AFTER_SAM 0x0004L + +// Background Task in GSM mode: Initialization. +#define D_GSM_BGD_MGT 0L + +#define D_MISC_CONFIG 1L + +// Half Rate vocoder and ched definitions. + +#define D_SD_MIN_THR_TCHHS 37L +#define D_MA_MIN_THR_TCHHS 344L +#define D_MD_MAX_THR_TCHHS 2175L +#define D_MD1_MAX_THR_TCHHS 138L +#define D_SD_AV_THR_TCHHS 1845L +#define D_WED_FIL_TC 0x7c00L +#define D_WED_FIL_INI 4650L +#define D_X_MIN 15L +#define D_X_MAX 23L +#define D_Y_MIN 703L +#define D_Y_MAX 2460L +#define D_SLOPE 135L +#define D_WED_DIFF_THRESHOLD 406L +#define D_MABFI_MIN_THR_TCHHS 5320L +#define D_LDT_HR -5 +#define D_MACCTRESH_HR 6500 +#define D_MACCTRESH1_HR 6500 +#define D_GU_HR 2620 +#define D_GO_HR 3700 +#define D_B_HR 182 +#define D_SM_HR -1608 +#define D_ATTMAX_HR 53 + +// Enhanced Full Rate vocoder and ched definitions. + +#define C_MLDT_EFR -4 +#define C_MACCTHRESH_EFR 8000 +#define C_MACCTHRESH1_EFR 8000 +#define C_GU_EFR 4522 +#define C_GO_EFR 6500 +#define C_B_EFR 174 +#define C_SM_EFR -878 +#define C_ATTMAX_EFR 53 +#define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED) +#define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED) +#define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED) +#define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED) + +// Integrated Data Services definitions. +#define D_MAX_OVSPD_UL 8 +// Detect frames containing 90% of 1s as synchro frames +#define D_SYNC_THRES 0x3f50 +// IDLE frames are only frames with 100 % of 1s +#define D_IDLE_THRES 0x4000 +#define D_M1_THRES 5 +#define D_MAX_OVSP_DL 8 + +#define D_FACCH_THR 0 +#define D_DSP_TEST 0 +#define D_VERSION_NUMBER 0 +#define D_TI_VERSION 0 + +// DSP ADRESSES +//-------------------- + +#define DB_SIZE (4*20L) // 4 pages of 20 words... + +#define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long +#define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long +#define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long +#define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long +#define NDB_ADR 0xFFD001A8L // NDB start address : 268 words +#define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words + +#define DB2_R_PAGE_0 0xFFD00184L +#define DB2_R_PAGE_1 0xFFD00188L
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/dsp_defty.h Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,490 @@ +/* + * This header file is a stripped-down version of l1_defty.h from TCS211, + * defining the DSP's API RAM shared memory interface. + */ + +typedef unsigned short API; +typedef signed short API_SIGNED; + +typedef struct +{ + API d_task_d; // (0) Downlink task command. + API d_burst_d; // (1) Downlink burst identifier. + API d_task_u; // (2) Uplink task command. + API d_burst_u; // (3) Uplink burst identifier. + API d_task_md; // (4) Downlink Monitoring (FB/SB) command. + API d_background; // (5) Background tasks + API d_debug; // (6) Debug/Acknowledge/general purpose word. + API d_task_ra; // (7) RA task command. + API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only. + // bit [0..7] -> b_fn_report, FN in the normalized reporting period. + // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning. + API d_ctrl_tch; // (9) Tch channel description. + // bit [0..3] -> b_chan_mode, channel mode. + // bit [4..5] -> b_chan_type, channel type. + // bit [6] -> reset SACCH + // bit [7] -> vocoder ON + // bit [8] -> b_sync_tch_ul, synchro. TCH/UL. + // bit [9] -> b_sync_tch_dl, synchro. TCH/DL. + // bit [10] -> b_stop_tch_ul, stop TCH/UL. + // bit [11] -> b_stop_tch_dl, stop TCH/DL. + // bit [12.13] -> b_tch_loop, tch loops A/B/C. + API hole; // (10) unused hole. + + API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send. + // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB + // bit [1.2] -> unused + // bit [3] -> b_apcdel: delays-register in NDB + // bit [4] -> b_afc: freq control register in DB + // bit [5..15] -> unused + API a_a5fn[2]; // (12..13) Encryption Frame number. + // word 0, bit [0..4] -> T2. + // word 0, bit [5..10] -> T3. + // word 1, bit [0..11] -> T1. + API d_power_ctl; // (14) Power level control. + API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb"). + API d_ctrl_system; // (16) Controle Register for RESET/RESUME. + // bit [0..2] -> b_tsq, training sequence. + // bit [3] -> b_bcch_freq_ind, BCCH frequency indication. + // bit [15] -> b_task_abort, DSP task abort command. +} +T_DB_MCU_TO_DSP; + +typedef struct +{ + API d_task_d; // (0) Downlink task command. + API d_burst_d; // (1) Downlink burst identifier. + API d_task_u; // (2) Uplink task command. + API d_burst_u; // (3) Uplink burst identifier. + API d_task_md; // (4) Downlink Monitoring (FB/SB) task command. + API d_background; // (5) Background tasks + API d_debug; // (6) Debug/Acknowledge/general purpose word. + API d_task_ra; // (7) RA task command. + + API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). + API a_pm[3]; // (12..14) Power measurement results, array of 3 words. + API a_sch[5]; // (15..19) Header + SB information, array of 5 words. +} +T_DB_DSP_TO_MCU; + +typedef struct +{ + // MISC Tasks + API d_dsp_page; + + // DSP status returned (DSP --> MCU). + API d_error_status; + + // RIF control (MCU -> DSP). + API d_spcx_rif; + + API d_tch_mode; // TCH mode register. + // bit [0..1] -> b_dai_mode. + // bit [2] -> b_dtx. + + API d_debug1; // bit 0 at 1 enable dsp f_tx delay for Omega + + API d_dsp_test; + + // Words dedicated to Software version (DSP code + Patch) + API d_version_number1; + API d_version_number2; + + API d_debug_ptr; + API d_debug_bk; + + API d_pll_config; + + // GSM/GPRS DSP Debug trace support + API p_debug_buffer; + API d_debug_buffer_size; + API d_debug_trace_type; + + // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3. + API d_dsp_state; + // 5 words are reserved for any possible mapping modification + API d_hole1_ndb[2]; + + API p_debug_amr; + + API d_hole2_ndb[1]; + API d_mcsi_select; + + // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations + API d_apcdel1_bis; + API d_apcdel2_bis; + + // New registers due to IOTA analog base band + API d_apcdel2; + API d_vbctrl2; + API d_bulgcal; + + // Analog Based Band + API d_afcctladd; + + API d_vbuctrl; + API d_vbdctrl; + API d_apcdel1; + API d_apcoff; + API d_bulioff; + API d_bulqoff; + API d_dai_onoff; + API d_auxdac; + + API d_vbctrl1; + + API d_bbctrl; + + // Monitoring tasks control (MCU <- DSP) + // FB task + API d_fb_det; // FB detection result. (1 for FOUND). + API d_fb_mode; // Mode for FB detection algorithm. + API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR). + + // SB Task + API a_sch26[5]; // Header + SB information, array of 5 words. + + API d_audio_gain_ul; + API d_audio_gain_dl; + + // Controller of the melody E2 audio compressor + API d_audio_compressor_ctrl; + + // AUDIO module + API d_audio_init; + API d_audio_status; + + // Audio tasks + // TONES (MCU -> DSP) + API d_toneskb_init; + API d_toneskb_status; + API d_k_x1_t0; + API d_k_x1_t1; + API d_k_x1_t2; + API d_pe_rep; + API d_pe_off; + API d_se_off; + API d_bu_off; + API d_t0_on; + API d_t0_off; + API d_t1_on; + API d_t1_off; + API d_t2_on; + API d_t2_off; + API d_k_x1_kt0; + API d_k_x1_kt1; + API d_dur_kb; + API d_shiftdl; + API d_shiftul; + + API d_aec_ctrl; + + API d_es_level_api; + API d_mu_api; + + // Melody Ringer module + API d_melo_osc_used; + API d_melo_osc_active; + API a_melo_note0[4]; + API a_melo_note1[4]; + API a_melo_note2[4]; + API a_melo_note3[4]; + API a_melo_note4[4]; + API a_melo_note5[4]; + API a_melo_note6[4]; + API a_melo_note7[4]; + + // selection of the melody format + API d_melody_selection; + + // Holes due to the format melody E1 + API a_melo_holes[3]; + + // Speech Recognition module + API d_sr_status; // status of the DSP speech reco task + API d_sr_param; // paramters for the DSP speech reco task: OOV threshold. + API d_sr_bit_exact_test; // bit exact test + API d_sr_nb_words; // number of words used in the speech recognition task + API d_sr_db_level; // estimate voice level in dB + API d_sr_db_noise; // estimate noise in dB + API d_sr_mod_size; // size of the model + API a_n_best_words[4]; // array of the 4 best words + API a_n_best_score[8]; // array of the 4 best scores (each score is 32 bits length) + + // Audio buffer + API a_dd_1[22]; // Header + DATA traffic downlink information, sub. chan. 1. + API a_du_1[22]; // Header + DATA traffic uplink information, sub. chan. 1. + + // V42bis module + API d_v42b_nego0; + API d_v42b_nego1; + API d_v42b_control; + API d_v42b_ratio_ind; + API d_mcu_control; + API d_mcu_control_sema; + + // Background tasks + API d_background_enable; + API d_background_abort; + API d_background_state; + API d_max_background; + API a_background_tasks[16]; + API a_back_task_io[16]; + + // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory) + API d_gea_mode_ovly; + API a_gea_kc_ovly[4]; + + // SYREN specific registers + API d_vbpop; + API d_vau_delay_init; + API d_vaud_cfg; + API d_vauo_onoff; + API d_vaus_vol; + API d_vaud_pll; + API d_hole3_ndb[1]; + + // word used for the init of USF threshold + API d_thr_usf_detect; + + // Encryption module + API d_a5mode; // Encryption Mode. + + API d_sched_mode_gprs_ovly; + + // 7 words are reserved for any possible mapping modification + API d_hole4_ndb[5]; + + // Ramp definition for Omega device + API a_ramp[16]; + + // CCCH/SACCH downlink information...(!!) + API a_cd[15]; // Header + CCCH/SACCH downlink information. + + // FACCH downlink information........(!!) + API a_fd[15]; // Header + FACCH downlink information. + + // Traffic downlink data frames......(!!) + API a_dd_0[22]; // Header + DATA traffic downlink information, sub. chan. 0. + + // CCCH/SACCH uplink information.....(!!) + API a_cu[15]; // Header + CCCH/SACCH uplink information. + + // FACCH downlink information........(!!) + API a_fu[15]; // Header + FACCH uplink information + + // Traffic downlink data frames......(!!) + API a_du_0[22]; // Header + DATA traffic uplink information, sub. chan. 0. + + // Random access.....................(MCU -> DSP). + API d_rach; // RACH information. + + //...................................(MCU -> DSP). + API a_kc[4]; // Encryption Key Code. + + // Integrated Data Services module + API d_ra_conf; + API d_ra_act; + API d_ra_test; + API d_ra_statu; + API d_ra_statd; + API d_fax; + API a_data_buf_ul[21]; + API a_data_buf_dl[37]; + + // GTT API mapping for DSP code 34 (for test only) + API d_tty_status; + API d_tty_detect_thres; + API d_ctm_detect_shift; + API d_tty_fa_thres; + API d_tty_mod_norm; + API d_tty_reset_buffer_ul; + API d_tty_loop_ctrl; + API p_tty_loop_buffer; + + API a_sr_holes0[414]; + + // new AEC + API d_cont_filter; + API d_granularity_att; + API d_coef_smooth; + API d_es_level_max; + API d_fact_vad; + API d_thrs_abs; + API d_fact_asd_fil; + API d_fact_asd_mut; + API d_far_end_pow_h; + API d_far_end_pow_l; + API d_far_end_noise_h; + API d_far_end_noise_l; + + // Speech recognition model + API a_sr_holes1[145]; + API d_cport_init; + API d_cport_ctrl; + API a_cport_cfr[2]; + API d_cport_tcl_tadt; + API d_cport_tdat; + API d_cport_tvs; + API d_cport_status; + API d_cport_reg_value; + + API a_cport_holes[1011]; + + API a_model[1041]; + + // EOTD buffer + API d_eotd_first; + API d_eotd_max; + API d_eotd_nrj_high; + API d_eotd_nrj_low; + API a_eotd_crosscor[18]; + // AMR ver 1.0 buffers + API a_amr_config[4]; + API a_ratscch_ul[6]; + API a_ratscch_dl[6]; + API d_amr_snr_est; // estimation of the SNR of the AMR speech block + API d_amms_ul_voc; + API d_thr_onset_afs; // thresh detection ONSET AFS + API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS + API d_thr_ratscch_afs; // thresh detection RATSCCH AFS + API d_thr_update_afs; // thresh detection SID_UPDATE AFS + API d_thr_onset_ahs; // thresh detection ONSET AHS + API d_thr_sid_ahs; // thresh detection SID frames AHS + API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER + API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA + API d_thr_soft_bits; + + API d_melody_e2_osc_stop; + API d_melody_e2_osc_active; + API d_melody_e2_semaphore; + API a_melody_e2_osc[16][3]; + API d_melody_e2_globaltimefactor; + API a_melody_e2_instrument_ptr[8]; + API d_melody_e2_deltatime; + + API a_d_macc_thr_afs[8]; + API a_d_macc_thr_ahs[6]; +} +T_NDB_MCU_DSP; + +typedef struct +{ + API_SIGNED d_transfer_rate; + + // Common GSM/GPRS + // These words specified the latencies to applies on some peripherics + API_SIGNED d_lat_mcu_bridge; + API_SIGNED d_lat_mcu_hom2sam; + API_SIGNED d_lat_mcu_bef_fast_access; + API_SIGNED d_lat_dsp_after_sam; + + // DSP Start address + API_SIGNED d_gprs_install_address; + + API_SIGNED d_misc_config; + + API_SIGNED d_cn_sw_workaround; + + API_SIGNED d_hole2_param[4]; + + //...................................Frequency Burst. + API_SIGNED d_fb_margin_beg; + API_SIGNED d_fb_margin_end; + API_SIGNED d_nsubb_idle; + API_SIGNED d_nsubb_dedic; + API_SIGNED d_fb_thr_det_iacq; + API_SIGNED d_fb_thr_det_track; + //...................................Demodulation. + API_SIGNED d_dc_off_thres; + API_SIGNED d_dummy_thres; + API_SIGNED d_dem_pond_gewl; + API_SIGNED d_dem_pond_red; + + //...................................TCH Full Speech. + API_SIGNED d_maccthresh1; + API_SIGNED d_mldt; + API_SIGNED d_maccthresh; + API_SIGNED d_gu; + API_SIGNED d_go; + API_SIGNED d_attmax; + API_SIGNED d_sm; + API_SIGNED d_b; + + // V42Bis module + API_SIGNED d_v42b_switch_hyst; + API_SIGNED d_v42b_switch_min; + API_SIGNED d_v42b_switch_max; + API_SIGNED d_v42b_reset_delay; + + //...................................TCH Half Speech. + API_SIGNED d_ldT_hr; + API_SIGNED d_maccthresh_hr; + API_SIGNED d_maccthresh1_hr; + API_SIGNED d_gu_hr; + API_SIGNED d_go_hr; + API_SIGNED d_b_hr; + API_SIGNED d_sm_hr; + API_SIGNED d_attmax_hr; + + //...................................TCH Enhanced FR Speech. + API_SIGNED c_mldt_efr; + API_SIGNED c_maccthresh_efr; + API_SIGNED c_maccthresh1_efr; + API_SIGNED c_gu_efr; + API_SIGNED c_go_efr; + API_SIGNED c_b_efr; + API_SIGNED c_sm_efr; + API_SIGNED c_attmax_efr; + + //...................................CHED + API_SIGNED d_sd_min_thr_tchfs; + API_SIGNED d_ma_min_thr_tchfs; + API_SIGNED d_md_max_thr_tchfs; + API_SIGNED d_md1_max_thr_tchfs; + + API_SIGNED d_sd_min_thr_tchhs; + API_SIGNED d_ma_min_thr_tchhs; + API_SIGNED d_sd_av_thr_tchhs; + API_SIGNED d_md_max_thr_tchhs; + API_SIGNED d_md1_max_thr_tchhs; + + API_SIGNED d_sd_min_thr_tchefs; + API_SIGNED d_ma_min_thr_tchefs; + API_SIGNED d_md_max_thr_tchefs; + API_SIGNED d_md1_max_thr_tchefs; + + API_SIGNED d_wed_fil_ini; + API_SIGNED d_wed_fil_tc; + API_SIGNED d_x_min; + API_SIGNED d_x_max; + API_SIGNED d_slope; + API_SIGNED d_y_min; + API_SIGNED d_y_max; + API_SIGNED d_wed_diff_threshold; + API_SIGNED d_mabfi_min_thr_tchhs; + + // FACCH module + API_SIGNED d_facch_thr; + + // IDS module + API_SIGNED d_max_ovsp_ul; + API_SIGNED d_sync_thres; + API_SIGNED d_idle_thres; + API_SIGNED d_m1_thres; + API_SIGNED d_max_ovsp_dl; + API_SIGNED d_gsm_bgd_mgt; + + // FIR coefficients + API a_fir_holes[4]; + API a_fir31_uplink[31]; + API a_fir31_downlink[31]; +} +T_PARAM_MCU_DSP; + +typedef struct +{ + API d_debug_ptr_begin; + API d_debug_ptr_end; +} +T_DB2_DSP_TO_MCU;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/leadapi.h Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,25 @@ +/* + * Definitions for the DSP boot and patch download mechanism, + * taken from leadapi.h in TCS211. + */ + +#define APIF_ADDR 0xFFD00000L +#define BASE_API_ARM APIF_ADDR /* API RAM for ARM */ +#define BASE_API_LEAD 0xE000 /* API RAM for Lead */ + +#define DOWNLOAD_EXT_PAGE (APIF_ADDR + 0x0FF8) /* Address of the extended DSP page of the */ +#define DOWNLOAD_SIZE (APIF_ADDR + 0x0FFA) /* Address of the download size variable */ +#define DOWNLOAD_ADDR (APIF_ADDR + 0x0FFC) /* Address of the download address variable */ +#define DOWNLOAD_STATUS (APIF_ADDR + 0x0FFE) /* Address of the download status variable */ + +/* Maximum size of a block which can be copied into the API RAM */ + +#define MAX_BLOCK_SIZE 0x7F0 +#define MAX_UINT 65535 + +/* Possible values for the download status */ + +#define LEAD_READY 1 +#define BLOCK_READY 2 +#define PROGRAM_DONE 3 +#define PAGE_SELECTION 4
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/main.c Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,18 @@ +#include "types.h" + +main() +{ + uart_select_init(); + printf("Calypso version ID program running\n"); + print_boot_rom_info(); + printf("Device ID code: 0x%04X\n", *(volatile u16 *)0xFFFEF000); + printf("Device version code: 0x%04X\n", *(volatile u16 *)0xFFFEF002); + printf("ARM ID code: 0x%04X\n", *(volatile u16 *)0xFFFFFE00); + printf("cDSP ID code: 0x%04X\n", *(volatile u16 *)0xFFFFFE02); + dsp_power_on(); + for (;;) { + putchar('='); + if (command_entry()) + command_dispatch(); + } +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/target-utils/calversion/mygetchar.c Wed Dec 26 06:40:02 2018 +0000 @@ -0,0 +1,21 @@ +/* + * The interactive command entry (editing) function in libcommon + * will call mygetchar() for its character input. It is supposed + * to be a blocking wait for input, but in some programs other + * processing can be done while waiting - for example, check for + * keypad presses as well. This is the basic version which waits + * for serial input and nothing else. + */ + +extern int serial_in_poll(); + +int +mygetchar() +{ + register int c; + + do + c = serial_in_poll(); + while (c < 0); + return c; +}