FreeCalypso > hg > freecalypso-tools
changeset 496:3d73d4d3527f
target-utils: removed osmo_delay_ms() from ABB access code
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Sat, 25 May 2019 20:17:27 +0000 |
parents | 06ad5e30e8d0 |
children | 74610c4f10f7 |
files | target-utils/libbase/abbdrv.c target-utils/libbase/spidrv.c |
diffstat | 2 files changed, 8 insertions(+), 5 deletions(-) [+] |
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line diff
--- a/target-utils/libbase/abbdrv.c Sat May 25 18:51:19 2019 +0000 +++ b/target-utils/libbase/abbdrv.c Sat May 25 20:17:27 2019 +0000 @@ -58,7 +58,8 @@ /* A read cycle contains two SPI transfers */ spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx); - osmo_delay_ms(1); + /* delay of seven 13MHz cycles */ + wait_ARM_cycles(7); spi_xfer(TWL3025_DEV_IDX, 16, &tx, &rx); rx >>= 6; @@ -85,10 +86,12 @@ abb_select_page(0); /* CLK13M enable */ abb_reg_write(TOGBR2, TOGBR2_ACTS); - osmo_delay_ms(1); + /* ABB_Wait_IBIC_Access() delay of 210 us */ + wait_ARM_cycles(210 * 13); /* for whatever reason we need to do this twice */ abb_reg_write(TOGBR2, TOGBR2_ACTS); - osmo_delay_ms(1); + /* ABB_Wait_IBIC_Access() delay of 210 us */ + wait_ARM_cycles(210 * 13); abb_state_initdone = 1; return(1); }
--- a/target-utils/libbase/spidrv.c Sat May 25 18:51:19 2019 +0000 +++ b/target-utils/libbase/spidrv.c Sat May 25 20:17:27 2019 +0000 @@ -120,8 +120,8 @@ else if (reg_status & SPI_STATUS_WE) break; } - /* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */ - osmo_delay_ms(1); + /* delay of seven 13MHz cycles */ + wait_ARM_cycles(7); if (din) { tmp = SPI_REGS.reg_rx_msb << 16;