FreeCalypso > hg > gsm-net-reveng
annotate tcsm2-notes/tr16 @ 28:9bcdb091c24d default tip
trau-decode: new program trau-hr-dump
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Sun, 18 Aug 2024 08:37:02 +0000 |
parents | 2daf8f209707 |
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rev | line source |
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2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
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1 TR16-S is the 16-channel transcoder card, providing 16 TRAU channels. |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
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2 Examination of the board reveals the following major components: |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
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3 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 Global for the whole TR16-S: |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 One Lattice ispLSI1032E: a programmable logic device, non-volatile configuration |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 bits inside. |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 One CY62128BLL-70SI chip: 128K x 8 static RAM. |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 Replicated 16x, one set for each TRAU channel: |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 One DSP chip, has these markings in addition to TI logo: |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 TRLPRB 1.1 |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 D36884PZ-66 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 ADW-4BAORLW |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 |
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Mychaela Falconia <falcon@freecalypso.org>
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19 I had no success in finding any documentation for this DSP chip - was it one of |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
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20 those semi-custom Skunkworks parts without public documentation? I surmise |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 (without any proof!) that it is probably based on C54x architecture. |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 In addition to this DSP, there is one more chip replicated 16x per channel, one |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 next to each DSP: IDT 71V016, 64K x 16 static RAM. |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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25 |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
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26 Note the absence of any flash or other non-volatile memory chips: there is |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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27 non-volatile storage of configuration bits inside the Lattic PLD, but that's |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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28 just logic, no code. The available documentation for TCSM2 strongly suggests |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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29 that operational DSP code is loaded from TRCO, presumably on each system boot, |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
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30 but what about boot code, how does the "cold" TR16-S card communicate with TRCO? |
2daf8f209707
tcsm2-notes: initial observations on boards
Mychaela Falconia <falcon@freecalypso.org>
parents:
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31 The custom DSP ASICs probably have some ROM in them, supporting boot and maybe |
2daf8f209707
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Mychaela Falconia <falcon@freecalypso.org>
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32 providing some common routines or tables for the operational code, who knows... |