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comparison chipsetsw/drivers/drv_core/abb/abb_inline.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /**********************************************************************************/
2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
3 /* */
4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
6 /* product is protected under copyright law and trade secret law as an */
7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
8 /* rights reserved. */
9 /* */
10 /* */
11 /* Filename : abb_inline.h */
12 /* */
13 /* Description : inline functions to drive the ABB device. */
14 /* The Serial Port Interface is used to connect the TI */
15 /* Analog BaseBand (ABB). */
16 /* It is assumed that the ABB is connected as the SPI */
17 /* device 0. */
18 /* */
19 /* Author : Pascal PUEL */
20 /* */
21 /* Version number : 1.0 */
22 /* */
23 /* Date and time : Dec 2002 */
24 /* */
25 /* Previous delta : Creation */
26 /* */
27 /**********************************************************************************/
28
29 #ifndef __ABB_INLINE_H__
30 #define __ABB_INLINE_H__
31
32 #include "l1sw.cfg"
33
34 #if (OP_L1_STANDALONE == 0)
35 #include "main/sys_types.h"
36 #else
37 #include "sys_types.h"
38 #endif
39
40 #include "spi/spi_drv.h"
41
42 // MACROS
43 #define ABB_WRITE_REG(reg, data) { \
44 SPI_WRITE_TX_MSB((data << 6) | reg) \
45 SPI_START_WRITE }
46
47 #define ABB_READ_REG(reg) { \
48 SPI_WRITE_TX_MSB(reg | 1) \
49 SPI_START_READ }
50
51
52 #define ABB_SET_PAGE(page) ABB_WRITE_REG(PAGEREG, page)
53
54 #define SEVEN_CYCLES_13M_NS 539
55
56 // INLINE FUNCTIONS
57 /*-----------------------------------------------------------------------*/
58 /* ABB_SetPage() */
59 /* */
60 /* This function sets the right page in the ABB register PAGEREG. */
61 /* */
62 /*-----------------------------------------------------------------------*/
63 static inline void ABB_SetPage(SYS_UWORD16 page)
64 {
65 volatile SYS_UWORD16 status;
66
67 ABB_SET_PAGE(page);
68 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & WE_ST) == 0);
69
70 // if IBIC is already processing another request (from the BSP)
71 // the USP request is delayed by 3 clock cycles
72 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
73 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
74 }
75
76
77 /*-----------------------------------------------------------------------*/
78 /* ABB_WriteRegister() */
79 /* */
80 /* This function writes "data" in the ABB register "abb_reg". */
81 /* */
82 /*-----------------------------------------------------------------------*/
83 static inline void ABB_WriteRegister(SYS_UWORD16 abb_reg, SYS_UWORD16 data)
84 {
85 volatile SYS_UWORD16 status;
86
87 ABB_WRITE_REG(abb_reg, data);
88 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & WE_ST) == 0);
89
90 // if IBIC is already processing another request (from the BSP)
91 // the USP request is delayed by 3 clock cycles
92 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
93 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
94
95 }
96
97
98 /*-----------------------------------------------------------------------*/
99 /* ABB_ReadRegister() */
100 /* */
101 /* This function reads the ABB register "abb_reg" and returns */
102 /* the real register value. */
103 /* */
104 /*-----------------------------------------------------------------------*/
105 static inline SYS_UWORD16 ABB_ReadRegister(SYS_UWORD16 abb_reg)
106 {
107 volatile SYS_UWORD16 status;
108
109 // First part of read access to the ABB register
110 ABB_READ_REG(abb_reg);
111 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & RE_ST) == 0);
112
113 // if IBIC is already processing another request (from the BSP)
114 // the USP request is delayed by 3 clock cycles
115 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
116 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
117
118 // Second part of read access to the ABB register
119 ABB_READ_REG(abb_reg);
120 while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & RE_ST) == 0);
121
122 // if IBIC is already processing another request (from the BSP)
123 // the USP request is delayed by 3 clock cycles
124 // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case
125 wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS));
126
127 return ((SPI_ReadRX_LSB() >> 6) & 0x3ff);
128 }
129
130
131 #endif // __ABB_INLINE_H__