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comparison chipsetsw/drivers/drv_core/memif/mem.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : mem.h
12
13 Description : Header file for the memory interface module
14
15 Project : Drivers
16
17 Author : proussel@ti.com Patrick Roussel.
18
19 Version number : 1.22
20
21 Date : 08/22/03
22
23 Previous delta : 12/19/00 14:24:11
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.mem.h
26
27 Sccs Id (SID) : '@(#) mem.h 1.12 01/30/01 10:22:24 '
28
29 *****************************************************************************/
30
31 #ifndef _MEM_H_
32 #define _MEM_H_
33
34 #include "l1sw.cfg"
35 #include "chipset.cfg"
36 #if (OP_L1_STANDALONE == 0)
37 #include "main/sys_types.h"
38 #else
39 #include "sys_types.h"
40 #endif
41
42
43 #define MEM_APIC_REG 0xffe00000 /* APIC register address */
44
45 #define MEM_STR1_ADDR 0xfffe0000 /* Strobe 1 : address */
46 #define MEM_STR1_CS 32 /* Strobe 1 : number of CS */
47 #define MEM_STR0_ADDR 0xffff0000 /* Strobe 0 : address */
48 #define MEM_STR0_CS 31 /* Strobe 0 : number of CS */
49
50
51 #define MEM_STR_LENGTH 2048 /* Strobe : length of a CS space */
52
53 #define MEM_UART_IRDA 0xFFFF5000
54 #define MEM_UART_MODEM 0xFFFF5800
55
56
57 #define MEM_RIF 0xFFFF7000
58
59 #if (OP_L1_STANDALONE == 0)
60 #define MEM_TCIF 0xFFFEA800
61 #define MEM_ICR 0xFFFEB000
62
63 /**** Generic masks ****/
64 #define BIT0 0x00000001L
65 #define BIT1 0x00000002L
66 #define BIT2 0x00000004L
67 #define BIT3 0x00000008L
68 #define BIT4 0x00000010L
69 #define BIT5 0x00000020L
70 #define BIT6 0x00000040L
71 #define BIT7 0x00000080L
72 #define BIT8 0x00000100L
73 #define BIT9 0x00000200L
74 #define BIT10 0x00000400L
75 #define BIT11 0x00000800L
76 #define BIT12 0x00001000L
77 #define BIT13 0x00002000L
78 #define BIT14 0x00004000L
79 #define BIT15 0x00008000L
80 #define BIT16 0x00010000L
81
82
83 #define MEM_DEV_ID0 0xFFFEF000
84 #define MEM_DEV_ID1 0xFFFEF002
85
86
87 // Register read and write macros.
88 #define READ_REGISTER_ULONG ( reg ) ( *(volatile unsigned long * const )( reg ) )
89 #define WRITE_REGISTER_ULONG ( reg, val ) ( *(volatile unsigned long * const )( reg ) ) = ( val )
90 #define READ_REGISTER_USHORT ( reg ) ( *(volatile unsigned short * const)( reg ) )
91 #define WRITE_REGISTER_USHORT( reg, val ) ( *(volatile unsigned short * const)( reg ) ) = ( val )
92 #define READ_REGISTER_UCHAR ( reg ) ( *(volatile unsigned char * const )( reg ) )
93 #define WRITE_REGISTER_UCHAR ( reg, val ) ( *(volatile unsigned char * const )( reg ) ) = ( val )
94 #endif /* OP_L1_STANDALONE == 0 */
95
96 /**** External memory register ****/
97 #define MEM_TIMER_ADDR 0xfffff800 /* TIMER control register */
98
99 #define MEM_RHEA_CNTL 0xfffff900 /* memory RHEA control register */
100 #define MEM_API_CNTL 0xfffff902 /* memory API control register */
101 #define MEM_ARM_RHEA 0xfffff904 /* memory ARM/RHEA control register */
102 #define ENHANCED_RHEA_CNTL 0xfffff906 /* memory ARM/RHEA control register */
103
104 #define MEM_INTH_ADDR 0xfffffa00 /* INTH registers addr. */
105 #define MEM_REG_ADDR 0xfffffb00 /* memory i/f registers addr. */
106 #define MEM_REG_nCS0 (MEM_REG_ADDR + 0) /* nCS0 register address */
107 #define MEM_REG_nCS1 (MEM_REG_ADDR + 2) /* nCS1 register address */
108 #define MEM_REG_nCS2 (MEM_REG_ADDR + 4) /* nCS2 register address */
109 #define MEM_REG_nCS3 (MEM_REG_ADDR + 6) /* nCS3 register address */
110
111 #if ((CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
112 #define MEM_REG_nCS4 (MEM_REG_ADDR + 8) /* nCS4 register address */
113 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
114 #define MEM_REG_nCS6 (MEM_REG_ADDR + 0xc) /* nCS6 register address */
115 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
116 #define MEM_REG_nCS4 (MEM_REG_ADDR + 0xa) /* nCS4 register address */
117 #define MEM_REG_nCS6 (MEM_REG_ADDR + 0xc) /* nCS6 register address */
118 #define MEM_REG_nCS7 (MEM_REG_ADDR + 0x8) /* nCS7 register address */
119 #else
120 #if (CHIPSET != 12)
121 #define MEM_REG_nCS4 (MEM_REG_ADDR + 8) /* nCS4 register address */
122 #define MEM_REG_nCS5 (MEM_REG_ADDR + 0xa) /* nCS5 register address */
123 #endif
124 #endif
125
126 #define MEM_CTRL_REG (MEM_REG_ADDR + 0xe) /* Control register address */
127
128 #if (CHIPSET != 12)
129 #define MEM_DMA_ADDR 0xfffffc00 /* DMA controller reg. addr. */
130 #define MEM_CLKM_ADDR 0xfffffd00 /* CLKM registers addr. */
131 #endif
132
133 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
134 #define MEM_DPLL_ADDR 0xffff9800 /* DPLL control register */
135 #endif
136
137 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
138 #define MEM_MPU_ADDR 0xFFFFFF00 /* Base address of MPU module */
139 #endif
140
141 #define RTC_XIO_START 0xfffe1800
142
143 #if (OP_L1_STANDALONE == 0)
144 #define ARM_CONF_REG 0xFFFEF006
145 #endif
146
147 #define MEM_SIM 0xFFFE0000
148 #define MEM_TSP 0xFFFE0800
149 #define MEM_TPU_REG 0xFFFE1000
150 #define MEM_TPU_RAM 0xFFFE1400
151 #define MEM_RTC 0xFFFE1800
152 #define MEM_ULPD 0xFFFE2000
153 #define MEM_SPI 0xFFFE3000
154 #define MEM_TIMER1 0xFFFE3800
155 #define MEM_UWIRE 0xFFFE4000
156 #define MEM_ARMIO 0xFFFE4800
157 #define MEM_TIMER2 0xFFFE6800
158 #define MEM_LPG 0xFFFE7800
159 #define MEM_PWL 0xFFFE8000
160 #define MEM_PWT 0xFFFE8800
161 #define MEM_JTAGID_PART 0xFFFEF000 /* JTAG ID code register */
162 #define MEM_JTAGID_VER 0xFFFEF002 /* JTAG ID code register */
163 #if (CHIPSET != 12)
164 #define MEM_IO_SEL 0xFFFEF00A
165 #endif
166
167 #if (CHIPSET != 12)
168 /**** External memory register ****/
169
170 #define MEM_REG_WS 0x001f /* number of wait states */
171 #define MEM_REG_DVS 0x0060 /* device size */
172 #define MEM_REG_WE 0x0080 /* write enable */
173 #define MEM_REG_BIG 0x0100 /* big endian */
174
175 #define MEM_DVS_8 0 /* device size = 8 bits */
176 #define MEM_DVS_16 1 /* device size = 16 bits */
177 #define MEM_DVS_32 2 /* device size = 32 bits */
178
179
180 #define MEM_WRITE_DIS 0 /* write disable */
181 #define MEM_WRITE_EN 1 /* write enable */
182
183 #define MEM_LITTLE 0 /* little endian */
184 #define MEM_BIG 1 /* big endian */
185
186 #define MEM_NO_ADAPT 0 /* no memory adaptation */
187 #define MEM_ADAPT 1 /* memory adaptation */
188
189 /**** Memory control register ****/
190
191 #define MEM_CNTL_0_BIG 0x01 /* Big Endian for strobe 0 */
192 #define MEM_CNTL_0_ADAP 0x02 /* size adaptation for strobe 0 */
193 #define MEM_CNTL_1_BIG 0x04 /* Big Endian for strobe 1 */
194 #define MEM_CNTL_1_ADAP 0x08 /* size adaptation for strobe 1 */
195 #define MEM_CNTL_API_BIG 0x10 /* Big Endian for API */
196 #define MEM_CNTL_API_ADAP 0x20 /* size adaptation for API */
197 #define MEM_CNTL_DBG 0x40 /* debug */
198 #endif /* (CHIPSET != 12)*/
199
200 #if (OP_L1_STANDALONE == 1)
201 #if (CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
202 // for CHIPSET 12, the structure is defined in sys_memif.h, with some added parameters
203 typedef struct {
204
205 /* CONF_CSx register configuration */
206 SYS_UWORD8 d_ws;
207 SYS_UWORD8 d_dvs;
208 SYS_UWORD8 d_we;
209 SYS_UWORD8 d_dc;
210
211 } T_MEMIF_CS_CONFIG;
212 #endif
213 #endif /* OP_L1_STANDALONE == 1 */
214 #define ARM_CLK_SRC 0x04
215 #define ARM_MCLK_DIV 0x30
216 #define TPU_CLK_ENABLE 0x400
217
218 #if (CHIPSET != 12)
219 #define ASIC_CONF 0xfffef008
220 #endif
221
222
223 // duplicate definition with MEM_ARMIO !!
224 //#define ARMIO_ADDR 0xfffe4800
225
226 /**** Config registers ****/
227 #if (CHIPSET != 12)
228 #define QUARTZ_REG 0xfffef00c
229
230
231 #define MEM_INIT_CS0(d_ws, d_dvs, d_we, d_dc) ( \
232 *((volatile SYS_UWORD16 *) MEM_REG_nCS0 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
233
234 #define MEM_INIT_CS1(d_ws, d_dvs, d_we, d_dc) ( \
235 *((volatile SYS_UWORD16 *) MEM_REG_nCS1 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
236
237 #define MEM_INIT_CS2(d_ws, d_dvs, d_we, d_dc) ( \
238 *((volatile SYS_UWORD16 *) MEM_REG_nCS2 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
239
240 #define MEM_INIT_CS3(d_ws, d_dvs, d_we, d_dc) ( \
241 *((volatile SYS_UWORD16 *) MEM_REG_nCS3 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
242
243 #define MEM_INIT_CS4(d_ws, d_dvs, d_we, d_dc) ( \
244 *((volatile SYS_UWORD16 *) MEM_REG_nCS4 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
245
246 #if ((CHIPSET == 3) || (CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
247 #define MEM_INIT_CS6(d_ws, d_dvs, d_we, d_dc) ( \
248 *((volatile SYS_UWORD16 *) MEM_REG_nCS6 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
249 #endif
250
251 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
252 #define MEM_INIT_CS7(d_ws, d_dvs, d_we, d_dc) ( \
253 *((volatile SYS_UWORD16 *) MEM_REG_nCS7 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
254 #endif
255
256 #endif /* endif (CHIPSET != 12)*/
257
258
259
260 #if (CHIPSET == 12)
261 #include "sys_map.h"
262
263 #define MEM_UART_MODEM2 C_MAP_UART_MODEM2_BASE
264 #define MEM_TIMER_SEC_ADDR C_MAP_WD_TIMER_SEC_BASE /* TIMER Secure control register */
265 #define MEM_MPU_ADDR C_MAP_EMPU_BASE /* Base address of MPU module */
266 #define MEM_KEYBOARD C_MAP_KEYBOARD_BASE
267 #if (OP_L1_STANDALONE == 0)
268 #define MEM_MMC_SD_IO C_MAP_MMC_SD_BASE
269
270 /* Address of the Random Number Generator */
271 #define MEM_RNG 0x09A00000
272 /* Address of the DES/3DES */
273 #define MEM_DES 0x09900000
274 #endif /* OP_L1_STANDALONE == 0 */
275 #endif /* CHIPSET == 12 */
276
277 #endif /* _MEM_H_ */
278