FreeCalypso > hg > tcs211-c139
annotate chipsetsw/layer1/tpu_drivers/source0/tpudrv12.h @ 22:68e6e5c455e0
C139 aftermarket FFS config
author | Mychaela Falconia <falcon@ivan.Harhan.ORG> |
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date | Sun, 01 Nov 2015 06:54:46 +0000 |
parents | ffee43b74949 |
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rev | line source |
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1 /****************** Revision Controle System Header *********************** |
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2 * GSM Layer 1 software |
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3 * Copyright (c) Texas Instruments 1998 |
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4 * |
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5 * Filename tpudrv12.h |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ****************** Revision Controle System Header ***********************/ |
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9 |
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10 //--- Configuration values |
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11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode |
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12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc |
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13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init" |
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14 // TeST - Enable Main VCO buffer for test |
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15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer |
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16 |
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17 #include "rf.cfg" |
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18 |
18
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checking in tpudrv12 source adapted for C139 in TCS211 environment
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19 #define CONFIG_TARGET_COMPAL 1 |
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20 #define USE_TSPACT2_FOR_TXLOW 1 |
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21 |
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22 //--- RITA PG declaration |
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23 |
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24 #define R_PG_10 0 |
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25 #define R_PG_13 1 |
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26 #define R_PG_20 2 // For RFPG 2.2, use 2.0 |
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27 #define R_PG_23 3 |
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28 |
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29 //--- PA declaration |
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30 #define PA_MGF9009 0 |
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31 #define PA_RF3146 1 |
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32 #define PA_RF3133 2 |
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33 #define PA_PF08123B 3 |
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34 #define PA_AWT6108 4 |
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35 |
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36 #if (RF_PA == PA_MGF9009 || RF_PA == PA_PF08123B) |
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37 #define PA_CTRL_INT 0 |
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38 #else |
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39 #define PA_CTRL_INT 1 |
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40 #endif |
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41 |
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42 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0 |
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43 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number) |
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44 // This is also used in l1_rf12.h to select the SWAP_IQ |
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45 #if (RF_PG >= R_PG_20) |
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46 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX |
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47 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around") |
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48 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds |
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49 #elif (RF_PG == R_PG_13) |
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50 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX |
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51 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around") |
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52 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds |
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53 #else |
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54 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX |
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55 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around") |
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56 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds |
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57 #endif |
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58 |
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59 //- Bit definitions for TST register programings, etc |
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60 #define BIT_0 0x000001 |
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61 #define BIT_1 0x000002 |
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62 #define BIT_2 0x000004 |
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63 #define BIT_3 0x000008 |
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64 #define BIT_4 0x000010 |
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65 #define BIT_5 0x000020 |
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66 #define BIT_6 0x000040 |
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67 #define BIT_7 0x000080 |
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68 #define BIT_8 0x000100 |
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69 #define BIT_9 0x000200 |
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70 #define BIT_10 0x000400 |
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71 #define BIT_11 0x000800 |
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72 #define BIT_12 0x001000 |
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73 #define BIT_13 0x002000 |
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74 #define BIT_14 0x004000 |
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75 #define BIT_15 0x008000 |
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76 #define BIT_16 0x010000 |
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77 #define BIT_17 0x020000 |
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78 #define BIT_18 0x040000 |
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79 #define BIT_19 0x080000 |
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80 #define BIT_20 0x100000 |
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81 #define BIT_21 0x200000 |
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82 #define BIT_22 0x400000 |
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83 #define BIT_23 0x800000 |
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84 |
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85 //--- TRF6151 definitions ------------------------------------------ |
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86 |
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87 //- BASE REGISTER definitions |
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88 #define REG_RX 0x000000 // MODE0 |
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89 #define REG_PLL 0x000001 // MODE1 |
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90 #define REG_PWR 0x000002 // MODE2 |
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91 #define REG_CFG 0x000003 // MODE3 |
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92 |
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93 //- TeST REGISTER definitions => Used for WA only |
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94 // TeST - PLL2 WA => Define PLL2 TEST register |
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95 #define TST_PLL2 0x00001E // MODE 14 |
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96 |
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97 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register |
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98 #define TST_VCO3 0x00000F // MODE 15 (0*16+15*1) |
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99 #define TST_VCO4 0x000024 // MODE 36 (2*16+4*1) |
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100 |
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101 // Alpha RF7 WA TeST registers |
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102 #define TST_LDO 0x000027 // MODE 39 (2*16+7*1) |
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103 #define TST_PLL1 0x00001D // MODE 29 (1*16+13*1) |
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104 #define TST_TX2 0x000037 // MODE 55 (3*16+7*1) |
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105 |
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106 // More Alpha RF7 WA TeST registers |
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107 #define TST_TX3 0x00003C // MODE 61 (3*16+12*1) |
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108 #define TST_TX4 0x00003D // MODE 61 (3*16+13*1) |
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109 |
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110 // PG 2.1 WA TeST registers |
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111 #define TST_PLL3 0x00001F // MODE 31 (1*16+15*1) |
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112 // #define TST_PLL4 0x00002C // MODE 44 (2*16+12*1) |
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113 #define TST_MISC 0x00003E // MODE 62 (3*16+14*1) => Used for setting the VCXO current |
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114 #define TST_LO 0x00001C // MODE 28 (1*16+12*1) |
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115 |
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diff
changeset
|
116 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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changeset
|
117 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that, |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
118 // when accessed, triggers the copy of the serial registers. |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
119 // This is necessary to switch into "manual operation mode" |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
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120 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
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121 #define TX_LOOP_MANUAL BIT_3 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
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|
122 |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
123 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
124 //- REG_RX - MODE0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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changeset
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125 #define BLOCK_DETECT_0 BIT_3 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
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126 #define BLOCK_DETECT_1 BIT_4 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
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127 #define RST_BLOCK_DETECT_0 BIT_5 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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128 #define RST_BLOCK_DETECT_1 BIT_6 |
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Space Falcon <falcon@ivan.Harhan.ORG>
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129 #define READ_EN BIT_7 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
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130 #define RX_CAL_MODE BIT_8 |
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Space Falcon <falcon@ivan.Harhan.ORG>
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diff
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131 #define RF_GAIN (BIT_10 | BIT_9) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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132 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
133 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
134 //- REG_PLL - MODE1 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
135 //PLL_REGB |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
136 //PLL_REGA |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
137 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
138 //- REG_PWR - MODE2 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
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139 #define BANDGAP_MODE_OFF 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
140 #define BANDGAP_MODE_ON_ENA BIT_4 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
141 #define BANDGAP_MODE_ON_DIS (BIT_4 | BIT_3) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
142 #define REGUL_MODE_ON BIT_5 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
143 // BIT[8..6] band |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
144 #define BAND_SELECT_GSM BIT_6 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
145 #define BAND_SELECT_DCS BIT_7 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
146 #define BAND_SELECT_850_LO BIT_8 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
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147 #define BAND_SELECT_850_HI (BIT_8 | BIT_6) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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changeset
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148 #define BAND_SELECT_PCS (BIT_8 | BIT_7) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
149 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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changeset
|
150 #define SYNTHE_MODE_OFF 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
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changeset
|
151 #define SYNTHE_MODE_RX BIT_9 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
152 #define SYNTHE_MODE_TX BIT_10 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
153 #define RX_MODE_OFF 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
154 #define RX_MODE_A BIT_11 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
155 #define RX_MODE_B1 BIT_12 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
156 #define RX_MODE_B2 (BIT_12 | BIT_11) |
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
157 #define TX_MODE_OFF 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
158 #define TX_MODE_ON BIT_13 |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
159 #define PACTRL_APC_OFF 0x0 |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
160 #define PACTRL_APC_ON BIT_14 |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
161 #define PACTRL_APC_DIS 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
162 #define PACTRL_APC_ENA BIT_15 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
163 |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
164 |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
165 //- REG_CFG - MODE3 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
166 // Common PA controller settings: |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
167 #define PACTRL_TYPE_PWR 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
168 #define PACTRL_TYPE_CUR BIT_3 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
169 #define PACTRL_IDIOD_30_UA 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
170 #define PACTRL_IDIOD_300_UA BIT_4 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
171 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
172 // PA controller Clara-like (Power Sensing) settings: |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
173 #define PACTRL_VHOME_610_MV (BIT_7 | BIT_5) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
174 #define PACTRL_VHOME_839_MV (BIT_7 | BIT_5) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
175 #define PACTRL_VHOME_1000_MV (BIT_6 | BIT_9) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
176 #define PACTRL_VHOME_1600_MV (BIT_8 | BIT_5) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
177 #define PACTRL_RES_OPEN 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
178 #define PACTRL_RES_150_K BIT_10 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
179 #define PACTRL_RES_300_K BIT_11 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
180 #define PACTRL_RES_NU (BIT_10 | BIT_11) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
181 #define PACTRL_CAP_0_PF 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
182 #define PACTRL_CAP_12_5_PF BIT_12 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
183 #define PACTRL_CAP_25_PF (BIT_13 | BIT_12) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
184 #define PACTRL_CAP_50_PF BIT_13 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
185 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
186 // PACTRL_CFG contains the configuration of the PACTRL that will |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
187 // be put into the REG_CFG register at initialization time |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
188 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
189 // in this #define!!! |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
190 #if (RF_PA == 0) // MGF9009 (LCPA) |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
191 #define PACTRL_CFG \ |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
192 PACTRL_IDIOD_300_UA | \ |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
193 PACTRL_CAP_25_PF | \ |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
194 PACTRL_VHOME_1000_MV | \ |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
195 PACTRL_RES_300_K |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
196 #elif (RF_PA == 1) // 3146 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
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|
197 #define PACTRL_CFG 0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
198 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
199 #elif (RF_PA == 2) // 3133 |
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Space Falcon <falcon@ivan.Harhan.ORG>
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diff
changeset
|
200 #define PACTRL_CFG 0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
201 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
202 #elif (RF_PA == 3) // PF08123B |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
203 #define PACTRL_CFG \ |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
204 PACTRL_TYPE_PWR | \ |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
205 PACTRL_CAP_50_PF | \ |
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initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
206 PACTRL_RES_300_K | \ |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
207 PACTRL_VHOME_610_MV |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
208 #elif (RF_PA == 4) // AWT6108 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
209 #define PACTRL_CFG 0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
210 #else |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
211 #error Unknown PA specifiec! |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
212 #endif |
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
213 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
214 // Temperature sensor |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
215 #define TEMP_SENSOR_OFF 0x0 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
216 #define TEMP_SENSOR_ON BIT_14 |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
217 // Internal Logic Init Disable |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
218 #define ILOGIC_INIT_DIS BIT_15 |
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
219 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register |
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
220 // It was introduced in PG 1.2 |
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
221 // For previous PGs this BIT was unused, so it can be safelly programmed |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
222 // for all PGs |
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
223 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
224 |
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
225 // RF signals connected to TSPACT [0..7] |
18
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
226 |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
227 #if CONFIG_TARGET_PIRELLI |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
228 #define RF_RESET_LINE BIT_5 |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
229 #else |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
230 #define RF_RESET_LINE BIT_0 |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
231 #endif |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
232 |
ffee43b74949
checking in tpudrv12 source adapted for C139 in TCS211 environment
Mychaela Falconia <falcon@ivan.Harhan.ORG>
parents:
0
diff
changeset
|
233 #define RF_SER_ON RF_RESET_LINE |
0
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
234 #define RF_SER_OFF 0 |
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235 |
18
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236 #define TEST_TX_ON 0 |
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237 #define TEST_RX_ON 0 |
0
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238 |
18
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239 #if CONFIG_TARGET_LEONARDO || CONFIG_TARGET_ESAMPLE |
0
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240 |
18
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241 // 4-band config (E-sample, P2, Leonardo) |
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242 #define FEM_7 BIT_2 // act2 |
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243 #define FEM_8 BIT_1 // act1 |
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244 #define FEM_9 BIT_4 // act4 |
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245 |
18
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246 #define PA_HI_BAND BIT_3 // act3 |
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247 #define PA_LO_BAND 0 |
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248 #define PA_OFF 0 |
0
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249 |
18
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250 #define FEM_PINS (FEM_7 | FEM_8 | FEM_9) |
0
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251 |
18
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252 #define FEM_OFF ( FEM_PINS ^ 0 ) |
0
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253 |
18
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254 #define FEM_SLEEP ( 0 ) |
0
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255 |
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256 // This configuration is always inverted. |
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257 |
18
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258 // RX_UP/DOWN and TX_UP/DOWN |
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259 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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260 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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261 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_7 ) |
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262 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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263 |
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264 #define RU_850 ( PA_OFF | FEM_PINS ^ FEM_9 ) |
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265 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 ) |
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266 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_7 ) |
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267 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 ) |
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268 |
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269 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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270 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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271 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_8 ) |
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272 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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273 |
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274 #define RU_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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275 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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276 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_8 ) |
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277 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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278 |
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279 #elif CONFIG_TARGET_GTAMODEM |
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280 |
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281 // Openmoko's triband configuration is a bastardized version |
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282 // of TI's quadband one from Leonardo/E-Sample |
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283 |
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284 #define FEM_7 BIT_2 // act2 |
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285 #define FEM_8 BIT_1 // act1 |
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286 #define FEM_9 BIT_4 // act4 |
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287 |
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288 #define PA_HI_BAND BIT_3 // act3 |
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289 #define PA_LO_BAND 0 |
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290 #define PA_OFF 0 |
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291 |
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292 #define FEM_PINS (FEM_7 | FEM_8 | FEM_9) |
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293 |
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294 #define FEM_OFF ( FEM_PINS ^ 0 ) |
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295 |
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296 #define FEM_SLEEP ( 0 ) |
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297 |
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298 // This configuration is always inverted. |
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299 |
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300 // RX_UP/DOWN and TX_UP/DOWN |
0
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301 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
302 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
303 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_9 ) |
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|
304 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
305 |
18
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306 #define RU_850 ( PA_OFF | FEM_PINS ^ 0 ) |
0
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|
307 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
308 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_9 ) |
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|
309 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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diff
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|
310 |
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|
311 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
312 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
313 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_7 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
314 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
315 |
18
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316 #define RU_1900 ( PA_OFF | FEM_PINS ^ FEM_8 ) |
0
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|
317 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
318 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_7 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
319 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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Space Falcon <falcon@ivan.Harhan.ORG>
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|
320 |
18
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|
321 #elif CONFIG_TARGET_PIRELLI |
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|
322 |
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|
323 #define ANTSW_RX_PCS BIT_4 |
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324 #define ANTSW_TX_HIGH BIT_10 |
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|
325 #define ANTSW_TX_LOW BIT_11 |
0
509db1a7b7b8
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diff
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|
326 |
18
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|
327 #define PA_HI_BAND BIT_3 // act3 |
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328 #define PA_LO_BAND 0 |
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329 #define PA_OFF 0 |
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|
330 |
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|
331 #define PA_ENABLE BIT_0 |
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|
332 |
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|
333 // Pirelli uses a non-inverting buffer |
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|
334 |
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|
335 #define FEM_OFF ( 0 ) |
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|
336 |
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changeset
|
337 #define FEM_SLEEP ( 0 ) |
0
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
338 |
18
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|
339 // RX_UP/DOWN and TX_UP/DOWN (triband) |
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0
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340 #define RU_900 ( PA_OFF | 0 ) |
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341 #define RD_900 ( PA_OFF | 0 ) |
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342 #define TU_900 ( PA_LO_BAND | ANTSW_TX_LOW ) |
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343 #define TD_900 ( PA_OFF | 0 ) |
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344 |
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345 #define RU_850 ( PA_OFF | 0 ) |
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346 #define RD_850 ( PA_OFF | 0 ) |
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347 #define TU_850 ( PA_LO_BAND | ANTSW_TX_LOW ) |
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348 #define TD_850 ( PA_OFF | 0 ) |
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349 |
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350 #define RU_1800 ( PA_OFF | 0 ) |
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351 #define RD_1800 ( PA_OFF | 0 ) |
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352 #define TU_1800 ( PA_HI_BAND | ANTSW_TX_HIGH ) |
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353 #define TD_1800 ( PA_OFF | 0 ) |
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354 |
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355 #define RU_1900 ( PA_OFF | ANTSW_RX_PCS ) |
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356 #define RD_1900 ( PA_OFF | 0 ) |
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357 #define TU_1900 ( PA_HI_BAND | ANTSW_TX_HIGH ) |
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358 #define TD_1900 ( PA_OFF | 0 ) |
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|
359 |
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360 #elif CONFIG_TARGET_COMPAL |
0
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361 |
18
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362 #define PA_HI_BAND BIT_8 // act8 |
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363 #define PA_LO_BAND 0 |
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364 #define PA_OFF 0 |
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365 |
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366 #define PA_ENABLE BIT_1 |
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|
367 |
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368 // FEM control signals are active low |
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369 #define FEM_PINS (BIT_6 | BIT_2) |
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370 |
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371 #define FEM_OFF ( FEM_PINS ^ 0 ) |
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|
372 |
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373 #define FEM_SLEEP ( 0 ) |
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374 |
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375 #define FEM_TX_HIGH BIT_6 |
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376 #if USE_TSPACT2_FOR_TXLOW |
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377 #define FEM_TX_LOW BIT_2 |
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378 #else |
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379 #define FEM_TX_LOW BIT_6 |
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changeset
|
380 #endif |
0
509db1a7b7b8
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diff
changeset
|
381 |
18
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382 // RX_UP/DOWN and TX_UP/DOWN |
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|
383 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
384 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
385 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW ) |
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changeset
|
386 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 ) |
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diff
changeset
|
387 |
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|
388 #define RU_850 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
389 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
390 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_TX_LOW ) |
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diff
changeset
|
391 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 ) |
0
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
392 |
18
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diff
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|
393 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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|
394 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
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diff
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|
395 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH ) |
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diff
changeset
|
396 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 ) |
0
509db1a7b7b8
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Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
397 |
18
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diff
changeset
|
398 #define RU_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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diff
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|
399 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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diff
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|
400 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_TX_HIGH ) |
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changeset
|
401 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 ) |
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diff
changeset
|
402 |
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0
diff
changeset
|
403 #endif // FreeCalypso target selection |
0
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
404 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
405 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0 |
18
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changeset
|
406 #if CONFIG_TARGET_PIRELLI |
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changeset
|
407 #define TC1_DEVICE_RF TC1_DEVICE1 // TSPEN1 |
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0
diff
changeset
|
408 #else |
0
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
409 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2 |
18
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0
diff
changeset
|
410 #endif |
0
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
411 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
412 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
413 //--- TIMINGS ---------------------------------------------------------- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
414 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
415 /*------------------------------------------*/ |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
416 /* Download delay values */ |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
417 /*------------------------------------------*/ |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
418 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
419 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
420 #define T TPU_CLOCK_RANGE |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
421 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
422 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
423 // - TPU instruction into TSP timings --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
424 // 1 tpu instruction = 1 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
425 #define DLT_1 1 // 1 tpu instruction = 1 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
426 #define DLT_2 2 // 2 tpu instruction = 2 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
427 #define DLT_3 3 // 3 tpu instruction = 3 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
428 #define DLT_4 4 // 4 tpu instruction = 4 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
429 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
430 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
431 // - Serialization timings --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
432 // The following values where calculated with Katrin Matthes... |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
433 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed, |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
434 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
435 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed, |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
436 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
437 // ... while the following values are based on the HYP004.doc document |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
438 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed, |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
439 // i.e. 12 / 6 qbit = 2 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
440 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed, |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
441 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
442 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
443 // - TPU command execution + serialization length --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
444 #define DLT_1B 4 // 3*move + serialization of 7 bits |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
445 #define DLT_2B 7 // 4*move + serialization of 2 bytes |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
446 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
447 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
448 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
449 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
450 // - INIT (delta or DLT) timings --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
451 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
452 #define DLT_I2 8 // Time required to set RF_SER_OFF |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
453 #define DLT_I3 5 // Time required to set RF_SER_ON |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
454 #define DLT_I4 110 // Regulator Turn-ON time |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
455 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
456 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
457 // - tdt & rdt --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
458 // MAX GSM (not GPRS) rdt and tdt values are... |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
459 //#define rdt 380 // MAX GSM rx delta timing |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
460 //#define tdt 400 // MAX GSM tx delta timing |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
461 // but current rdt and tdt values are... |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
462 #define rdt 0 // rx delta timing |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
463 #define tdt 0 // tx delta timing |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
464 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
465 // - RX timings --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
466 // - RX down: |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
467 // The times below are offsets to when BDLENA goes down |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
468 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
469 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
470 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
471 // - RX up: |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
472 // The times below are offsets to when BDLENA goes high |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
473 // Burst data comes here |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
474 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
475 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
476 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
477 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
478 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
479 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
480 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
481 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
482 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
483 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
484 // - TX timings --- |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
485 // - TX down: |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
486 // The times below are offsets to when BULENA goes down |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
487 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
488 #if (PA_CTRL_INT == 1) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
489 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
490 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF. |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
491 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN. |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
492 #endif |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
493 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
494 #if (PA_CTRL_INT == 0) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
495 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
496 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
497 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
498 #endif |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
499 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
500 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
501 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
502 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
503 // - TX up: |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
504 // The times below are offsets to when BULENA goes high |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
505 //burst data comes here |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
506 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
507 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
508 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
509 #if (PA_CTRL_INT == 0) |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
510 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
511 #endif |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
512 |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
513 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
514 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
515 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
516 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
517 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
518 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
519 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
520 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode" |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
521 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation" |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
522 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode" |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
523 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
524 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel |
509db1a7b7b8
initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff
changeset
|
525 |