FreeCalypso > hg > tcs211-c139

annotate chipsetsw/drivers/drv_app/ffs/board/amdsbdrv.c @ 48:616f63f3e501 default tip

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fixed bug in etm_pkt_send() dealing with max-sized packets: this fix is needed for fc-fsio cpout command to work like it does with Pirelli's firmware (they must have made the same fix)
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Fri, 13 Nov 2015 19:11:07 +0000
parents 509db1a7b7b8
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /******************************************************************************
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2 * Flash File System (ffs)
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
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4 *
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5 * FFS AMD single bank low level flash driver RAM code
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6 *
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7 * $Id: amdsbdrv.c 1.5.1.3 Tue, 06 Jan 2004 10:57:45 +0100 tsj $
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8 *
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9 ******************************************************************************/
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10
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11 #include "ffs.cfg"
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12
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13 #include "ffs/ffs.h"
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14 #include "ffs/board/drv.h"
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15 #include "ffs/board/ffstrace.h"
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16
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17
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18 // Due to long branches, we disable all tracing and led function calls.
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19 #undef tlw
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20 #define tlw(contents)
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21 #undef ttw
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22 #define ttw(contents)
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23
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24
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25 asm(" .label _ffsdrv_ram_amd_begin");
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26 asm(" .def _ffsdrv_ram_amd_begin");
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27
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28
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29 // IMPORTANT! Apparently, placing the int_disable/enable() function code
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30 // here instead of at the bottom of the file, makes the code crash or
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31 // freeze. Reason is as of yet unknown.
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32
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33 uint32 amd_int_disable(void);
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34 void amd_int_enable(uint32 tmp);
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35
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36
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37 /******************************************************************************
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38 * AMD Single Bank Driver Functions
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39 ******************************************************************************/
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40
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41 void ffsdrv_ram_amd_sb_write_halfword(volatile uint16 *addr, uint16 value)
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42 {
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43 volatile char *flash = dev.base;
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44 uint32 cpsr;
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45
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46 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
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47
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48 if (~*addr & value) {
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49 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
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50 return;
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51 }
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52
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53 cpsr = amd_int_disable();
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54 tlw(led_on(LED_WRITE));
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55
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56 flash[0xAAAA] = 0xAA; // AMD unlock cycle 1
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57 flash[0x5555] = 0x55; // AMD unlock cycle 2
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58 flash[0xAAAA] = 0xA0;
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59 *addr = value;
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60
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61 while ((*addr ^ value) & 0x80)
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62 ;
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63
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64 tlw(led_off(LED_WRITE));
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65 amd_int_enable(cpsr);
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66 }
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67
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68 // This VERY simple way of erase suspension only works because we run under
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69 // a pre-emptive operating system, so whenever an interrupt occurs, another
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70 // task takes the CPU, and at the end of the interrupt, FFS gets the CPU
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71 // again.
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72 void ffsdrv_ram_amd_sb_erase(uint8 block)
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73 {
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74 volatile char *flash = dev.base;
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75 volatile char *addr;
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76 uint32 cpsr;
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77 uint16 flashpoll;
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78
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79 addr = block2addr(block);
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80
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81 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
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82
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83 cpsr = amd_int_disable();
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84 tlw(led_on(LED_ERASE));
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85
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86 flash[0xAAAA] = 0xAA; // AMD unlock cycle 1
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87 flash[0x5555] = 0x55; // AMD unlock cycle 2
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88 flash[0xAAAA] = 0x80;
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89 flash[0xAAAA] = 0xAA; // AMD unlock cycle 1
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90 flash[0x5555] = 0x55; // AMD unlock cycle 2
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91 *addr = 0x30; // AMD erase sector command
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92
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93 // Wait for erase to finish.
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94 while ((*addr & 0x80) == 0) {
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95 tlw(led_toggle(LED_ERASE));
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96 // Poll interrupts, taking interrupt mask into account.
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97 if (INT_REQUESTED)
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98 {
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99 // 1. suspend erase
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100 // 2. enable interrupts
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101 // .. now the interrupt code executes
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102 // 3. disable interrupts
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103 // 4. resume erase
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104
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105 tlw(led_on(LED_ERASE_SUSPEND));
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106 *addr = 0xB0;
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107
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108 // wait for erase suspend to finish
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109 while ((*addr & 0x80) == 0)
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110 ;
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111
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112 tlw(led_off(LED_ERASE_SUSPEND));
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113 amd_int_enable(cpsr);
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114
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115 // Other interrupts and tasks run now...
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116
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117 cpsr = amd_int_disable();
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118 tlw(led_on(LED_ERASE_SUSPEND));
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119
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120 // Before resuming erase we must? check if the erase is really
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121 // suspended or if it did finish
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122 flashpoll = *addr;
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123 *addr = 0x30;
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124
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125 tlw(led_off(LED_ERASE_SUSPEND));
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126 }
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127 }
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128
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129 tlw(led_on(LED_ERASE));
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130 tlw(led_off(LED_ERASE));
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131 amd_int_enable(cpsr);
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132 }
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133
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134
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135 /******************************************************************************
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136 * Interrupt Enable/Disable
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137 ******************************************************************************/
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138
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139 uint32 amd_int_disable(void)
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
140 {
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
141 asm(" .state16");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
142 asm(" mov A1, #0xC0");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
143 asm(" ldr A2, tct_amd_disable");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
144 asm(" bx A2 ");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
145
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
146 asm("tct_amd_disable .field _TCT_Control_Interrupts+0,32");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
147 asm(" .global _TCT_Control_Interrupts");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
148 }
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
149
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
150 void amd_int_enable(uint32 cpsr)
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
151 {
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
152 asm(" .state16");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
153 asm(" ldr A2, tct_amd_enable");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
154 asm(" bx A2 ");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
155
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
156 asm("tct_amd_enable .field _TCT_Control_Interrupts+0,32");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
157 asm(" .global _TCT_Control_Interrupts");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
158 }
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
159
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
160 // Even though we have this end label, we cannot determine the number of
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
161 // constant/PC-relative data following the code!
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
162 asm(" .state32");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
163 asm(" .label _ffsdrv_ram_amd_end");
509db1a7b7b8 initial import: leo2moko-r1
Space Falcon <falcon@ivan.Harhan.ORG>
parents:
diff changeset
164 asm(" .def _ffsdrv_ram_amd_end");