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comparison chipsetsw/drivers/drv_core/dma/sys_dma.c @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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1 /* @(#) nom : sys_dma.c SID: 1.2 date : 05/23/03 */
2 /* Filename: sys_dma.c */
3 /* Version: 1.2 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Guillaume Leterrier
10 * Francois Amand
11 *
12 *
13 * Important Note
14 * --------------
15 *
16 * This S/W is a preliminary version. It contains information on a product
17 * under development and is issued for evaluation purposes only. Features
18 * characteristics, data and other information are subject to change.
19 *
20 * The S/W is furnished under Non Disclosure Agreement and may be used or
21 * copied only in accordance with the terms of the agreement. It is an offence
22 * to copy the software in any way except as specifically set out in the
23 * agreement. No part of this document may be reproduced or transmitted in any
24 * form or by any means, electronic or mechanical, including photocopying and
25 * recording, for any purpose without the express written permission of Texas
26 * Instruments Inc.
27 *
28 ******************************************************************************
29 *
30 * FILE NAME: sys_dma.c
31 *
32 *
33 * PURPOSE: DMA drivers for CALYPSO PLUS.
34 * The drivers allows DMA module configuration and control.
35 *
36 *
37 * FILE REFERENCES:
38 *
39 * Name IO Description
40 * ------------- -- ---------------------------------------------
41 *
42 *
43 *
44 * EXTERNAL VARIABLES:
45 *
46 * Source:
47 *
48 * Name Type IO Description
49 * ------------- --------------- -- ------------------------------
50 *
51 *
52 *
53 * EXTERNAL REFERENCES:
54 *
55 * Name Description
56 * ------------------ -------------------------------------------------------
57 *
58 *
59 *
60 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
61 *
62 *
63 *
64 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
65 *
66 *
67 *
68 * NOTES:
69 *
70 *
71 *
72 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
73 *
74 *
75 *
76 *
77 * DEVELOPMENT HISTORY:
78 *
79 * Date Name(s) Version Description
80 * ----------- -------------- ------- -------------------------------------
81 * 23-Oct-2002 G.Leterrier 0.0.1 First implementation
82 * 6-Feb-2003 G.Leterrier 0.0.2 Reset HW request to 0, before new setup in function "f_dma_channel_parameter_set"
83 * 20-Feb-2003 G.Leterrier 0.0.3 f_dma_global_parameter_set correction on API priority bit
84 * disable and clear status register channel before re-configuration
85 * ALGORITHM:
86 *
87 *
88 *****************************************************************************/
89
90 #include "chipset.cfg"
91
92 #if (CHIPSET == 12)
93
94 #include "sys_dma.h"
95
96
97 /***************************************************************************/
98 /* global variable
99 *****************************************************************************/
100
101 extern T_DMA_CALL_BACK pf_dma_call_back_address[C_DMA_NUMBER_OF_CHANNEL];
102
103 /******************************************************************************
104 *
105 * FUNCTION NAME: f_dma_get_version_driver
106 * This functionis used to get to DMA driver software version.
107 *
108 * ARGUMENT LIST:
109 *
110 * Argument Type IO Description
111 * ---------- ---------- -- -------------------------------------------
112 * none
113 *
114 *
115 * RETURN VALUE: SYS_UWORD16
116 *
117 *****************************************************************************/
118 SYS_UWORD16 f_dma_get_version_driver(void)
119 {
120 return(C_DMA_VERSION_DRIVER);
121 } /*f_dma_get_version_driver()*/
122
123 /******************************************************************************
124 *
125 * FUNCTION NAME:f_dma_global_parameter_set
126 * The function is used to setup the DMA global configuration.
127 *
128 *
129 * ARGUMENT LIST:
130 *
131 * Argument Type IO Description
132 * ---------- ---------- -- -------------------------------------------
133 * p_dma_global_parameter T_DMA_TYPE_GLOBAL_PARAMETER* I Pointer on data structure containing all global parameter of DMA configuration
134 *
135 *
136 *
137 * RETURN VALUE: None
138 *
139 *****************************************************************************/
140 void f_dma_global_parameter_set(T_DMA_TYPE_GLOBAL_PARAMETER *p_dma_global_parameter)
141 {
142 if (p_dma_global_parameter->d_dma_global_auto_gate==C_DMA_AUTO_GATE_ON)
143 {
144 C_DMA_GCR_REG |= (C_DMA_AUTO_GATE_ON << C_DMA_GCR_AUTO_GATE_POS );
145 }
146
147 else
148 {
149 C_DMA_GCR_REG &= ~( C_DMA_GCR_AUTO_GATE_MASK << C_DMA_GCR_AUTO_GATE_POS );
150 }
151
152 C_DMA_AR_REG = (
153 (p_dma_global_parameter->d_dma_global_api_prio << C_DMA_AR_API_PRIO_POS)
154 | (p_dma_global_parameter->d_dma_global_rhea_prio << C_DMA_AR_RHEA_PRIO_POS)
155 | (p_dma_global_parameter->d_dma_global_imif_prio << C_DMA_AR_IMIF_PRIO_POS)
156 );
157 } /*f_dma_global_parameter_set() */
158
159 /******************************************************************************
160 *
161 * FUNCTION NAME: f_dma_channel_allocation_set
162 * This function defines the allocation of a channel.
163 * This function is used to set which channel can be configured through the ARM and which one can be configured through the DSP.
164 *
165 *
166 *
167 * ARGUMENT LIST:
168 *
169 * Argument Type IO Description
170 * ---------- ---------- -- -------------------------------------------
171 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable providing the channel number
172 * d_dma_channel_allocation T_DMA_TYPE_CHANNEL_ALLOCATION I Variable defining if the channel allocated to the ARM or the DSP.
173 *
174 *
175 *
176 * RETURN VALUE: None
177 *
178 *****************************************************************************/
179 void f_dma_channel_allocation_set(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number, T_DMA_TYPE_CHANNEL_ALLOCATION d_dma_channel_allocation)
180 {
181 if (d_dma_channel_allocation==C_DMA_CHANNEL_DSP)
182 {
183 C_DMA_CAR_REG |= (C_DMA_CHANNEL_DSP << d_dma_channel_number);
184 }
185
186 else
187 {
188 C_DMA_CAR_REG &= ~( C_DMA_CHANNEL_DSP << d_dma_channel_number );
189 }
190
191
192 } /*f_dma_channel_allocation_set */
193
194 /******************************************************************************
195 *
196 * FUNCTION NAME: f_dma_channel_parameter_set
197 * The function is used to setup a DMA channel configuration.
198 *
199 *
200 * ARGUMENT LIST:
201 *
202 * Argument Type IO Description
203 * ---------- ---------- -- -------------------------------------------
204 * p_dma_channel_parameter T_DMA_TYPE_CHANNEL_PARAMETER * I Pointer on data structure containing all the parameter to setup a channel
205 *
206 *
207 *
208 * RETURN VALUE: None
209 *
210 *****************************************************************************/
211 void f_dma_channel_parameter_set(T_DMA_TYPE_CHANNEL_PARAMETER *p_dma_channel_parameter)
212 {
213 SYS_UWORD16 d_temp_register;
214
215 F_DMA_CHANNEL_DISABLE(p_dma_channel_parameter->d_dma_channel_number);
216
217 d_temp_register=F_DMA_GET_CHANNEL_IT_STATUS(p_dma_channel_parameter->d_dma_channel_number);
218
219 pf_dma_call_back_address[p_dma_channel_parameter->d_dma_channel_number]=p_dma_channel_parameter->pf_dma_call_back_address;
220
221
222
223 if (p_dma_channel_parameter->d_dma_channel_secured==C_DMA_CHANNEL_SECURED)
224 {
225 C_DMA_SCR_REG |= (C_DMA_CHANNEL_SECURED << p_dma_channel_parameter->d_dma_channel_number);
226 }
227
228 else
229 {
230 C_DMA_SCR_REG &= ~( C_DMA_CHANNEL_SECURED << p_dma_channel_parameter->d_dma_channel_number );
231 }
232
233 C_DMA_CSDP_REG(p_dma_channel_parameter->d_dma_channel_number) = (
234
235 (p_dma_channel_parameter->d_dma_channel_data_type << C_DMA_CSDP_DATA_TYPE_POS )
236 | (p_dma_channel_parameter->d_dma_channel_src_port << C_DMA_CSDP_SRC_POS )
237 | (p_dma_channel_parameter->d_dma_src_channel_packed << C_DMA_CSDP_SRC_PACK_POS )
238 | (p_dma_channel_parameter->d_dma_src_channel_burst_en << C_DMA_CSDP_SRC_BURST_EN_POS )
239 | (p_dma_channel_parameter->d_dma_channel_dst_port << C_DMA_CSDP_DST_POS )
240 | (p_dma_channel_parameter->d_dma_dst_channel_packed << C_DMA_CSDP_DST_PACK_POS )
241 | (p_dma_channel_parameter->d_dma_dst_channel_burst_en << C_DMA_CSDP_DST_BURST_EN_POS )
242 );
243
244 C_DMA_CCR_REG(p_dma_channel_parameter->d_dma_channel_number) &= ~C_DMA_CCR_SYNC_MASK;
245
246
247
248 C_DMA_CCR_REG(p_dma_channel_parameter->d_dma_channel_number) = (
249
250 (p_dma_channel_parameter->d_dma_channel_hw_synch << C_DMA_CCR_SYNC_POS )
251 | (p_dma_channel_parameter->d_dma_channel_priority << C_DMA_CCR_PRIO_POS )
252 | (p_dma_channel_parameter->d_dma_channel_auto_init << C_DMA_CCR_AUTO_INIT_POS )
253 | (p_dma_channel_parameter->d_dma_channel_fifo_flush << C_DMA_CCR_FIFO_FLUSH_POS )
254 | (p_dma_channel_parameter->d_dma_src_channel_addr_mode << C_DMA_CCR_SRC_AMODE_POS )
255 | (p_dma_channel_parameter->d_dma_dst_channel_addr_mode << C_DMA_CCR_DST_AMODE_POS )
256 );
257
258 C_DMA_CICR_REG(p_dma_channel_parameter->d_dma_channel_number) = (
259
260 (p_dma_channel_parameter->d_dma_channel_it_time_out << C_DMA_CICR_TOUT_IE_POS )
261 | (p_dma_channel_parameter->d_dma_channel_it_drop << C_DMA_CICR_DROP_IE_POS )
262 | (p_dma_channel_parameter->d_dma_channel_it_frame <<C_DMA_CICR_FRAME_IE_POS )
263 | (p_dma_channel_parameter->d_dma_channel_it_block << C_DMA_CICR_BLOCK_IE_POS )
264 | (p_dma_channel_parameter->d_dma_channel_it_half_block << C_DMA_CICR_HALF_BLOCK_IE_POS )
265 );
266
267 C_DMA_CSSA_L_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_src_address ); /* is a mask requested ? */
268
269
270 C_DMA_CSSA_U_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_src_address >> 16 ); /* is a mask requested ? */
271
272
273 C_DMA_CDSA_L_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_dst_address); /* is a mask requested ? */
274
275
276 C_DMA_CDSA_U_REG(p_dma_channel_parameter->d_dma_channel_number)= (p_dma_channel_parameter->d_dma_channel_dst_address >> 16 ); /* is a mask requested ? */
277
278 C_DMA_CEN_REG(p_dma_channel_parameter->d_dma_channel_number) = (p_dma_channel_parameter->d_dma_channel_element_number );
279
280 C_DMA_CFN_REG(p_dma_channel_parameter->d_dma_channel_number) = (p_dma_channel_parameter->d_dma_channel_frame_number );
281
282
283 } /*f_dma_channel_parameter_set() */
284
285 /******************************************************************************
286 *
287 * FUNCTION NAME: f_dma_channel_enable
288 * This function is used to enable a DMA transfer of a channel which could be depending on a hardware request.
289 * If there is no hardware request, the transfer starts immediately.
290 *
291 * ARGUMENT LIST:
292 *
293 * Argument Type IO Description
294 * ---------- ---------- -- -------------------------------------------
295 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is enabled.
296 *
297 *
298 *
299 * RETURN VALUE: None
300 *
301 *****************************************************************************/
302 void f_dma_channel_enable (T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number)
303 {
304 F_DMA_CHANNEL_ENABLE(d_dma_channel_number);
305 }/* f_dma_channel_enable() */
306
307 /******************************************************************************
308 *
309 * FUNCTION NAME: f_dma_channel_disable
310 * This function is used to disable a DMA transfer of a channel
311 *
312 *
313 * ARGUMENT LIST:
314 *
315 * Argument Type IO Description
316 * ---------- ---------- -- -------------------------------------------
317 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is disabled.
318 *
319 *
320 *
321 * RETURN VALUE: None
322 *
323 *****************************************************************************/
324 void f_dma_channel_disable(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number)
325 {
326 F_DMA_CHANNEL_DISABLE(d_dma_channel_number);
327 } /*f_dma_channel_disable() */
328
329 /******************************************************************************
330 *
331 * FUNCTION NAME: f_dma_channel_auto_init_disable
332 * This function is disabling the auto-initialization mode of the channel.
333 * The channel completes the current transfer and stops.
334 *
335 * ARGUMENT LIST:
336 *
337 * Argument Type IO Description
338 * ---------- ---------- -- -------------------------------------------
339 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is disabled from auto-init mode.
340 *
341 *
342 * RETURN VALUE: None
343 *
344 *****************************************************************************/
345 void f_dma_channel_auto_init_disable(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number)
346 {
347 F_DMA_CHANNEL_AUTO_INIT_DISABLE(d_dma_channel_number);
348 } /* f_dma_channel_auto_init_disable */
349
350 /******************************************************************************
351 *
352 * FUNCTION NAME: f_dma_get_channel_counter
353 * This function can be used to monitor address
354 * where the last data of a frame has been written.
355 * This function provides only the lowest16 bits of the address.
356 *
357 *
358 * ARGUMENT LIST:
359 *
360 * Argument Type IO Description
361 * ---------- ---------- -- -------------------------------------------
362 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define from which channel, we get the counter.
363 *
364 * RETURN VALUE: None
365 *
366 *****************************************************************************/
367 SYS_UWORD16 f_dma_get_channel_counter(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number)
368 {
369 return(F_DMA_GET_CHANNEL_COUNTER(d_dma_channel_number));
370 } /*f_dma_get_channel_counter() */
371
372 /******************************************************************************
373 *
374 * FUNCTION NAME: f_dma_channel_soft_reset
375 * perform a soft reset of the following parameter of the channel :
376 * Source address,Destination address,Element number,Frame number,Channel counter
377 *
378 *
379 *
380 * ARGUMENT LIST:
381 *
382 * Argument Type IO Description
383 * ---------- ---------- -- -------------------------------------------
384 * d_dma_channel_number T_DMA_TYPE_CHANNEL_NUMBER I Variable to define which channel is soft reset.
385 *
386 *
387 * RETURN VALUE: None
388 *
389 *****************************************************************************/
390 void f_dma_channel_soft_reset(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number)
391 {
392 C_DMA_SRR_REG |= ( 0x1 << d_dma_channel_number);
393
394 while (C_DMA_SRR_REG & ( 0x1 << d_dma_channel_number)) /* wait for the reset is completed */
395 {
396 }
397
398 } /*f_dma_channel_soft_reset() */
399 #endif /* (CHIPSET == 12) */