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comparison chipsetsw/drivers/drv_core/dma/sys_dma.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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1 /* @(#) nom : sys_dma.h SID: 1.2 date : 05/23/03 */
2 /* Filename: sys_dma.h */
3 /* Version: 1.2 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Guillaume Leterrier
10 * Francois Amand
11 *
12 *
13 * Important Note
14 * --------------
15 *
16 * This S/W is a preliminary version. It contains information on a product
17 * under development and is issued for evaluation purposes only. Features
18 * characteristics, data and other information are subject to change.
19 *
20 * The S/W is furnished under Non Disclosure Agreement and may be used or
21 * copied only in accordance with the terms of the agreement. It is an offence
22 * to copy the software in any way except as specifically set out in the
23 * agreement. No part of this document may be reproduced or transmitted in any
24 * form or by any means, electronic or mechanical, including photocopying and
25 * recording, for any purpose without the express written permission of Texas
26 * Instruments Inc.
27 *
28 ******************************************************************************
29 *
30 * FILE NAME: sys_dma.h
31 *
32 *
33 * PURPOSE: Include file to use the DMA drivers for CALYPSO PLUS.
34 * The drivers allows DMA module configuration and control.
35 *
36 *
37 * FILE REFERENCES:
38 *
39 * Name IO Description
40 * ------------- -- ---------------------------------------------
41 *
42 *
43 *
44 * EXTERNAL VARIABLES:
45 *
46 * Source:
47 *
48 * Name Type IO Description
49 * ------------- --------------- -- ------------------------------
50 *
51 *
52 *
53 * EXTERNAL REFERENCES:
54 *
55 * Name Description
56 * ------------------ -------------------------------------------------------
57 *
58 *
59 *
60 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
61 *
62 *
63 *
64 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
65 *
66 *
67 *
68 * NOTES:
69 *
70 *
71 *
72 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
73 *
74 *
75 *
76 *
77 * DEVELOPMENT HISTORY:
78 *
79 * Date Name(s) Version Description
80 * ----------- -------------- ------- -------------------------------------
81 * 23-Oct-2002 Francois AMAND 0.0.1 First implementation
82 * 23-Oct-2002 G.Leterrier 0.0.2 Type, prototype definition
83 * 6-Dec-2002 G.Leterrier 0.0.3 remove base address
84 * 24-Feb-2003 G.Leterrier 0.0.4 change base address include name
85 * ALGORITHM:
86 * ALGORITHM:
87 *
88 *
89 *****************************************************************************/
90
91
92 #ifndef __SYS_DMA_H__
93 #define __SYS_DMA_H__
94
95 #include "l1sw.cfg"
96 #include "chipset.cfg"
97
98 #if (CHIPSET == 12)
99
100 #if (OP_L1_STANDALONE == 0)
101 #include "main/sys_types.h"
102 #else
103 #include "sys_types.h"
104 #endif
105
106 #include "sys_map.h"
107
108 /****************************************************************************
109 * CONSTANT DEFINITION
110 ***************************************************************************/
111
112
113
114
115 #define C_DMA_VERSION_DRIVER 0x0001
116
117 #define C_DMA_NUMBER_OF_CHANNEL 6
118
119 /*
120 * Registers offset definition
121 */
122
123 #define C_DMA_CHANNEL_SELECT_POS 6
124
125 /* Global registers */
126 #define C_DMA_GCR_OFFSET 0x0400
127 #define C_DMA_ISR_OFFSET 0x0402
128 #define C_DMA_CAR_OFFSET 0x0404
129 #define C_DMA_SCR_OFFSET 0x0406
130 #define C_DMA_SRR_OFFSET 0x0408
131 #define C_DMA_AR_OFFSET 0x040A
132
133 /* Channel registers */
134 #define C_DMA_CSDP_OFFSET(d_channel_index) (0x0000 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
135 #define C_DMA_CCR_OFFSET(d_channel_index) (0x0002 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
136 #define C_DMA_CICR_OFFSET(d_channel_index) (0x0004 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
137 #define C_DMA_CSR_OFFSET(d_channel_index) (0x0006 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
138 #define C_DMA_CSSA_L_OFFSET(d_channel_index) (0x0008 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
139 #define C_DMA_CSSA_U_OFFSET(d_channel_index) (0x000A + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
140 #define C_DMA_CDSA_L_OFFSET(d_channel_index) (0x000C + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
141 #define C_DMA_CDSA_U_OFFSET(d_channel_index) (0x000E + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
142 #define C_DMA_CEN_OFFSET(d_channel_index) (0x0010 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
143 #define C_DMA_CFN_OFFSET(d_channel_index) (0x0012 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
144 #define C_DMA_CPC_OFFSET(d_channel_index) (0x0018 + (d_channel_index << C_DMA_CHANNEL_SELECT_POS))
145
146
147 /*
148 * Registers address definition
149 */
150 /* Global registers */
151 #define C_DMA_GCR_REG * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_GCR_OFFSET)
152 #define C_DMA_ISR_REG * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_ISR_OFFSET)
153 #define C_DMA_CAR_REG * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CAR_OFFSET)
154 #define C_DMA_SCR_REG * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_SCR_OFFSET)
155 #define C_DMA_SRR_REG * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_SRR_OFFSET)
156 #define C_DMA_AR_REG * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_AR_OFFSET)
157
158 /* Channel registers */
159 #define C_DMA_CSDP_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSDP_OFFSET(d_channel_index))
160 #define C_DMA_CCR_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CCR_OFFSET(d_channel_index))
161 #define C_DMA_CICR_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CICR_OFFSET(d_channel_index))
162 #define C_DMA_CSR_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSR_OFFSET(d_channel_index))
163 #define C_DMA_CSSA_L_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSSA_L_OFFSET(d_channel_index))
164 #define C_DMA_CSSA_U_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CSSA_U_OFFSET(d_channel_index))
165 #define C_DMA_CDSA_L_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CDSA_L_OFFSET(d_channel_index))
166 #define C_DMA_CDSA_U_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CDSA_U_OFFSET(d_channel_index))
167 #define C_DMA_CEN_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CEN_OFFSET(d_channel_index))
168 #define C_DMA_CFN_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CFN_OFFSET(d_channel_index))
169 #define C_DMA_CPC_REG(d_channel_index) * (volatile SYS_UWORD16 *) (C_MAP_DMA_BASE + C_DMA_CPC_OFFSET(d_channel_index))
170
171
172
173 /*
174 * DMA_GCR register definition
175 */
176 /* Bits position in the register */
177 #define C_DMA_GCR_FREE_POS 2
178 #define C_DMA_GCR_AUTO_GATE_POS 3
179
180 /* Mask of the field in the register */
181 #define C_DMA_GCR_FREE_MASK 0x0001
182 #define C_DMA_GCR_AUTO_GATE_MASK 0x0001
183
184
185
186 /*
187 * DMA_AR register definition
188 */
189 /* Bits position in the register */
190 #define C_DMA_AR_IMIF_PRIO_POS 0
191 #define C_DMA_AR_RHEA_PRIO_POS 3
192 #define C_DMA_AR_API_PRIO_POS 4
193
194 /* Mask of the field in the register */
195 #define C_DMA_AR_IMIF_PRIO_MASK 0x0007
196 #define C_DMA_AR_RHEA_PRIO_MASK 0x0001
197 #define C_DMA_AR_API_PRIO_MASK 0x0001
198
199
200 /*
201 * DMA_CSDP register definition
202 */
203 /* Bits position in the register */
204 #define C_DMA_CSDP_DATA_TYPE_POS 0
205 #define C_DMA_CSDP_SRC_POS 2
206 #define C_DMA_CSDP_SRC_PACK_POS 6
207 #define C_DMA_CSDP_SRC_BURST_EN_POS 7
208 #define C_DMA_CSDP_DST_POS 9
209 #define C_DMA_CSDP_DST_PACK_POS 13
210 #define C_DMA_CSDP_DST_BURST_EN_POS 14
211
212 /* Mask of the field in the register */
213 #define C_DMA_CSDP_DATA_TYPE_MASK 0x0003
214 #define C_DMA_CSDP_SRC_MASK 0x000F
215 #define C_DMA_CSDP_SRC_PACK_MASK 0x0001
216 #define C_DMA_CSDP_SRC_BURST_EN_MASK 0x0003
217 #define C_DMA_CSDP_DST_MASK 0x000F
218 #define C_DMA_CSDP_DST_PACK_MASK 0x0001
219 #define C_DMA_CSDP_DST_BURST_EN_MASK 0x0003
220
221
222 /*
223 * DMA_CCR register definition
224 */
225 /* Bits position in the register */
226 #define C_DMA_CCR_SYNC_POS 0
227 #define C_DMA_CCR_PRIO_POS 6
228 #define C_DMA_CCR_EN_POS 7
229 #define C_DMA_CCR_AUTO_INIT_POS 8
230 #define C_DMA_CCR_FIFO_FLUSH_POS 10
231 #define C_DMA_CCR_SRC_AMODE_POS 12
232 #define C_DMA_CCR_DST_AMODE_POS 14
233
234 /* Mask of the field in the register */
235 #define C_DMA_CCR_SYNC_MASK 0x001F
236 #define C_DMA_CCR_PRIO_MASK 0x0001
237 #define C_DMA_CCR_EN_MASK 0x0001
238 #define C_DMA_CCR_AUTO_INIT_MASK 0x0001
239 #define C_DMA_CCR_FIFO_FLUSH_MASK 0x0001
240 #define C_DMA_CCR_SRC_AMODE_MASK 0x0003
241 #define C_DMA_CCR_DST_AMODE_MASK 0x0003
242
243
244 /*
245 * DMA_CICR register definition
246 */
247 /* Bits position in the register */
248 #define C_DMA_CICR_TOUT_IE_POS 0
249 #define C_DMA_CICR_DROP_IE_POS 1
250 #define C_DMA_CICR_FRAME_IE_POS 3
251 #define C_DMA_CICR_BLOCK_IE_POS 5
252 #define C_DMA_CICR_HALF_BLOCK_IE_POS 6
253
254 /* Mask of the field in the register */
255 #define C_DMA_CICR_TOUT_IE_MASK 0x0001
256 #define C_DMA_CICR_DROP_IE_MASK 0x0001
257 #define C_DMA_CICR_FRAME_IE_MASK 0x0001
258 #define C_DMA_CICR_BLOCK_IE_MASK 0x0001
259 #define C_DMA_CICR_HALF_BLOCK_IE_MASK 0x0001
260
261
262 /*
263 * DMA_CSR register definition
264 */
265 /* Bits position in the register */
266 #define C_DMA_CSR_TOUT_POS 0
267 #define C_DMA_CSR_DROP_POS 1
268 #define C_DMA_CSR_FRAME_POS 3
269 #define C_DMA_CSR_BLOCK_POS 5
270 #define C_DMA_CSR_SYNC_POS 6
271 #define C_DMA_CSR_HALF_BLOCK_POS 7
272 #define C_DMA_CSR_TOUT_SRC_NDST_POS 8
273
274 /* Mask of the field in the register */
275 #define C_DMA_CSR_TOUT_MASK 0x0001
276 #define C_DMA_CSR_DROP_MASK 0x0001
277 #define C_DMA_CSR_FRAME_MASK 0x0001
278 #define C_DMA_CSR_BLOCK_MASK 0x0001
279 #define C_DMA_CSR_SYNC_MASK 0x0001
280 #define C_DMA_CSR_HALF_BLOCK_MASK 0x0001
281 #define C_DMA_CSR_TOUT_SRC_NDST_MASK 0x0001
282
283
284
285 /****************************************************************************
286 * TYPE DEFINITION
287 ***************************************************************************/
288
289 /*
290 * Channel number definition
291 */
292 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_NUMBER;
293 #define C_DMA_CHANNEL_0 0
294 #define C_DMA_CHANNEL_1 1
295 #define C_DMA_CHANNEL_2 2
296 #define C_DMA_CHANNEL_3 3
297 #define C_DMA_CHANNEL_4 4
298 #define C_DMA_CHANNEL_5 5
299
300
301
302 #define C_DMA_CHANNEL_0_MASK 0x01
303 #define C_DMA_CHANNEL_1_MASK 0x02
304 #define C_DMA_CHANNEL_2_MASK 0x04
305 #define C_DMA_CHANNEL_3_MASK 0x08
306 #define C_DMA_CHANNEL_4_MASK 0x10
307 #define C_DMA_CHANNEL_5_MASK 0x20
308
309
310 /*
311 * Channel secure parameter definition
312 */
313 /* channel secured, must be used with crypto module */
314
315 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_SECURED;
316 #define C_DMA_CHANNEL_NOT_SECURED 0
317 #define C_DMA_CHANNEL_SECURED 1
318
319 /*
320 * Channel data type definition
321 */
322
323 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_DATA_TYPE;
324 #define C_DMA_DATA_S8 0 /* byte definition */
325 #define C_DMA_DATA_S16 1 /* half word definition */
326 #define C_DMA_DATA_S32 2 /* word definition */
327
328
329
330 /*
331 * Port definition
332 */
333
334
335 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_PORT;
336 #define C_DMA_IMIF_PORT 0 /* IMIF PORT definition */
337 #define C_DMA_RHEA_PORT 1 /* RHEA PORT definition */
338 #define C_DMA_API_PORT 2 /* API PORT definition */
339
340
341
342 /*
343 * port packing definition
344 */
345 /* port is performing packing to increase bandwidth if possible */
346
347 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_PACKED;
348 #define C_DMA_CHANNEL_NOT_PACKED 0
349 #define C_DMA_CHANNEL_PACKED 1
350
351
352 /*
353 * port transfer busrt/single definition
354 */
355
356
357 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_BURST_EN;
358 #define C_DMA_CHANNEL_SINGLE 0 /* port transfer Single */
359 #define C_DMA_CHANNEL_BURST4 2 /* port transfer burst 4 bytes, only IMIF can manage it */
360
361
362 /*
363 * Channel synchronisation definition
364 */
365
366 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_HW_SYNCH;
367 #define C_DMA_CHANNEL_NO_SYNCH 0 /* No Synch means software synchronisation */
368 #define C_DMA_CHANNEL_RIF_TX 1
369 #define C_DMA_CHANNEL_RIF_RX 2
370 #define C_DMA_CHANNEL_LCD 3
371 #define C_DMA_CHANNEL_UART_MODEM1_TX 4
372 #define C_DMA_CHANNEL_UART_MODEM1_RX 5
373 #define C_DMA_CHANNEL_UART_MODEM2_TX 6
374 #define C_DMA_CHANNEL_UART_MODEM2_RX 7
375 #define C_DMA_CHANNEL_UART_IRDA_TX 8
376 #define C_DMA_CHANNEL_UART_IRDA_RX 9
377 #define C_DMA_CHANNEL_USB_RX1 10
378 #define C_DMA_CHANNEL_USB_TX1 11
379 #define C_DMA_CHANNEL_USB_RX2 12
380 #define C_DMA_CHANNEL_USB_TX2 13
381 #define C_DMA_CHANNEL_USB_RX3 14
382 #define C_DMA_CHANNEL_USB_TX3 15
383 #define C_DMA_CHANNEL_MMC_SD_RX 16
384 #define C_DMA_CHANNEL_MMC_SD_TX 17
385 #define C_DMA_CHANNEL_MS_RX_TX 18
386 #define C_DMA_CHANNEL_USIM_RX 19
387 #define C_DMA_CHANNEL_USIM_TX 20
388 #define C_DMA_CHANNEL_UWIRE_RX_TX 23
389 #define C_DMA_CHANNEL_NAND_FLASH 24
390 #define C_DMA_CHANNEL_I2C_RX 25
391 #define C_DMA_CHANNEL_I2C_TX 26
392 #define C_DMA_CHANNEL_SHA1_TX 27 // channel must be set as secured channel
393 #define C_DMA_CHANNEL_DES_RX 28 // channel must be set as secured channel
394 #define C_DMA_CHANNEL_DES_TX 29 // channel must be set as secured channel
395 #define C_DMA_CHANNEL_CPORT_RX 30
396 #define C_DMA_CHANNEL_CPORT_TX 31
397
398
399 /*
400 * Channel priority definition
401 */
402
403 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_PRIORITY;
404 #define C_DMA_CHANNEL_PRIORITY_LOW 0 /* channel priority low */
405 #define C_DMA_CHANNEL_PRIORITY_HIGH 1 /* channel priority high */
406
407
408 /*
409 * Channel auto-initialisation definition
410 */
411 /* channel auto-init on, transfer restart on next HW request */
412
413 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_AUTO_INIT;
414 #define C_DMA_CHANNEL_AUTO_INIT_OFF 0
415 #define C_DMA_CHANNEL_AUTO_INIT_ON 1
416
417
418 /*
419 * Channel fifo-flush control
420 */
421
422
423 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_FIFO_FLUSH;
424 #define C_DMA_CHANNEL_FIFO_FLUSH_OFF 0 /* nothing happens on fifo */
425 #define C_DMA_CHANNEL_FIFO_FLUSH_ON 1 /* fifo is flushed */
426
427 /*
428 * definition addressng mode of source/destination port
429 */
430
431 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_ADDR_MODE;
432 #define C_DMA_CHANNEL_ADDR_MODE_CONSTANT 0 /* constant address */
433 #define C_DMA_CHANNEL_ADDR_MODE_POST_INC 1 /* post-increment address */
434 #define C_DMA_CHANNEL_ADDR_MODE_FRAME_INDEX 2 /* frame indexed address */
435
436
437 /*
438 * Channel interrupt event definition
439 */
440
441
442 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_IT_TIME_OUT;
443 #define C_DMA_CHANNEL_IT_TIME_OUT_OFF 0
444 #define C_DMA_CHANNEL_IT_TIME_OUT_ON 1 /* time out event on a port*/
445
446
447 /* drop event if new HW request issued, before completion of previous one */
448 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_IT_DROP;
449 #define C_DMA_CHANNEL_IT_DROP_OFF 0
450 #define C_DMA_CHANNEL_IT_DROP_ON 1
451
452
453 /* frame interrupt event */
454 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_IT_FRAME;
455 #define C_DMA_CHANNEL_IT_FRAME_OFF 0
456 #define C_DMA_CHANNEL_IT_FRAME_ON 1
457
458
459 /* end of block transfer event */
460 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_IT_BLOCK;
461 #define C_DMA_CHANNEL_IT_BLOCK_OFF 0
462 #define C_DMA_CHANNEL_IT_BLOCK_ON 1
463
464
465 /* half of block transfer event */
466 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_IT_HALF_BLOCK;
467 #define C_DMA_CHANNEL_IT_HALF_BLOCK_OFF 0
468 #define C_DMA_CHANNEL_IT_HALF_BLOCK_ON 1
469
470
471 /*
472 * DMA Definition of channel enable/disable
473 */
474
475 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_ENABLE;
476 #define C_DMA_CHANNEL_ENABLE_OFF 0
477 #define C_DMA_CHANNEL_ENABLE_ON 1
478
479
480
481
482 /*
483 * DMA Definition of free mode for emulation
484 */
485
486 typedef SYS_UWORD8 T_DMA_TYPE_FREE;
487 #define C_DMA_FREE_OFF 0
488 #define C_DMA_FREE_ON 1
489
490 /* In FREE_ON , on-going transfers are not stopped
491 when DMA receives the "suspend" signal from the processor */
492
493
494
495 /*
496 * DMA Definition of auto-gating clock
497 */
498
499 typedef SYS_UWORD8 T_DMA_TYPE_AUTO_GATE;
500 #define C_DMA_AUTO_GATE_OFF 0 /* DMA clock always ON */
501 #define C_DMA_AUTO_GATE_ON 1 /* DMA cut off clock according to activity */
502
503
504 /*
505 * priority definition on API port
506 */
507
508
509 typedef SYS_UWORD8 T_DMA_TYPE_API_PRIO;
510 #define C_DMA_API_PRIO_DMA 0 /* DMA has priority */
511 #define C_DMA_API_PRIO_ARM 1 /* ARM has priority */
512
513
514 /*
515 * priority definition on RHEA port
516 */
517
518
519 typedef SYS_UWORD8 T_DMA_TYPE_RHEA_PRIO;
520 #define C_DMA_RHEA_PRIO_DMA 0 /* DMA has priority */
521 #define C_DMA_RHEA_PRIO_ARM 1 /* ARM has priority */
522
523
524
525
526 /*
527 * priority definition on IMIF port
528 */
529
530 /* defines the number of consecutive cycles that are allocates to the CPU before DMA steals one cycle*/
531
532 typedef SYS_UWORD8 T_DMA_TYPE_IMIF_PRIO;
533 #define C_DMA_IMIF_PRIO_CPU_0 0
534 #define C_DMA_IMIF_PRIO_CPU_1 1
535 #define C_DMA_IMIF_PRIO_CPU_2 2
536 #define C_DMA_IMIF_PRIO_CPU_3 3
537 #define C_DMA_IMIF_PRIO_CPU_4 4
538 #define C_DMA_IMIF_PRIO_CPU_5 5
539 #define C_DMA_IMIF_PRIO_CPU_6 6
540 #define C_DMA_IMIF_PRIO_CPU_7 7
541
542
543 /*
544 * Definition of channel allocation between the DSP and ARM
545 */
546
547
548 typedef SYS_UWORD8 T_DMA_TYPE_CHANNEL_ALLOCATION;
549 #define C_DMA_CHANNEL_ARM 0 /* channel reserved to ARM */
550 #define C_DMA_CHANNEL_DSP 1 /* channel reserved to DSP */
551
552
553 /*
554 * Type definition of pointer for call back function
555 */
556
557
558 typedef void (*T_DMA_CALL_BACK) (SYS_UWORD16);
559
560 /****************************************************************************
561 * MACRO DEFINITION
562 ***************************************************************************/
563
564
565
566 /* enable free mode of dma */
567 #define F_DMA_SUSPEND_MODE_EMULATION_FREE_ENABLE C_DMA_GCR_REG |= (C_DMA_FREE_ON << C_DMA_GCR_FREE_POS )
568
569
570
571 /*disable free mode of the dma */
572 #define F_DMA_SUSPEND_MODE_EMULATION_FREE_DISABLE C_DMA_GCR_REG &= ~( C_DMA_GCR_FREE_MASK << C_DMA_GCR_FREE_POS )
573
574
575 /*enable channel transfer*/
576 #define F_DMA_CHANNEL_ENABLE(d_dma_channel_number) C_DMA_CCR_REG(d_dma_channel_number) |= (C_DMA_CHANNEL_ENABLE_ON << C_DMA_CCR_EN_POS )
577
578
579 /*disable channel transfer*/
580 #define F_DMA_CHANNEL_DISABLE(d_dma_channel_number) C_DMA_CCR_REG(d_dma_channel_number) &= ~(C_DMA_CCR_EN_MASK << C_DMA_CCR_EN_POS )
581
582
583 /*disable channel auto-initialisation mode*/
584 #define F_DMA_CHANNEL_AUTO_INIT_DISABLE(d_dma_channel_number) C_DMA_CCR_REG(d_dma_channel_number) &= ~(C_DMA_CCR_AUTO_INIT_MASK << C_DMA_CCR_AUTO_INIT_POS )
585
586
587 /* get channel counter */
588 #define F_DMA_GET_CHANNEL_COUNTER(d_dma_channel_number) C_DMA_CPC_REG(d_dma_channel_number)
589
590
591 /* get channel interrupt status, cleared after read. must be saved in a variable if re-use*/
592 #define F_DMA_GET_CHANNEL_IT_STATUS(d_dma_channel_number) C_DMA_CSR_REG(d_dma_channel_number)
593
594
595 /* compare if interruption status is time_out event on source */
596 #define F_DMA_COMPARE_CHANNEL_IT_STATUS_TIME_OUT_SRC(d_dma_status_it) ((C_DMA_CSR_TOUT_MASK & (d_dma_status_it >>C_DMA_CSR_TOUT_POS)) & (C_DMA_CSR_TOUT_SRC_NDST_MASK & (d_dma_status_it >>C_DMA_CSR_TOUT_SRC_NDST_POS)))
597
598
599 /* compare if interruption status is time_out event on destination */
600 #define F_DMA_COMPARE_CHANNEL_IT_STATUS_TIME_OUT_DST(d_dma_status_it) ((C_DMA_CSR_TOUT_MASK & (d_dma_status_it >>C_DMA_CSR_TOUT_POS)) & ( C_DMA_CSR_TOUT_SRC_NDST_MASK & ((~d_dma_status_it) >>C_DMA_CSR_TOUT_SRC_NDST_POS)))
601
602
603
604 /* compare if interruption status is drop event ( new hw event, before completion of the previous one */
605 #define F_DMA_COMPARE_CHANNEL_IT_STATUS_DROP(d_dma_status_it) (C_DMA_CSR_DROP_MASK & (d_dma_status_it >>C_DMA_CSR_DROP_POS))
606
607
608
609 /* compare if interruption status is an end of frame transfer event*/
610 #define F_DMA_COMPARE_CHANNEL_IT_STATUS_FRAME(d_dma_status_it) (C_DMA_CSR_FRAME_MASK & (d_dma_status_it >>C_DMA_CSR_FRAME_POS))
611
612
613
614 /* compare if interruption status is an end of block transfer event*/
615 #define F_DMA_COMPARE_CHANNEL_IT_STATUS_BLOCK(d_dma_status_it) (C_DMA_CSR_BLOCK_MASK & (d_dma_status_it >>C_DMA_CSR_BLOCK_POS))
616
617
618
619 /* compare if interruption status is an end of half_block transfer event*/
620 #define F_DMA_COMPARE_CHANNEL_IT_STATUS_HALF_BLOCK(d_dma_status_it) (C_DMA_CSR_HALF_BLOCK_MASK & (d_dma_status_it >>C_DMA_CSR_HALF_BLOCK_POS))
621
622
623 /****************************************************************************
624 * STRUCTURE DEFINITION
625 ***************************************************************************/
626
627
628
629 /* definition of parameter structure for global configuration */
630
631 typedef struct
632 {
633 T_DMA_TYPE_AUTO_GATE d_dma_global_auto_gate;
634 T_DMA_TYPE_API_PRIO d_dma_global_api_prio;
635 T_DMA_TYPE_RHEA_PRIO d_dma_global_rhea_prio;
636 T_DMA_TYPE_IMIF_PRIO d_dma_global_imif_prio;
637 }
638 T_DMA_TYPE_GLOBAL_PARAMETER;
639
640
641 /* definition of parameter structure for channel configuration */
642
643
644 typedef struct
645
646 {
647 T_DMA_CALL_BACK pf_dma_call_back_address;
648 //void (*pf_dma_call_back_address) (SYS_UWORD16); /* call back function address for interrupt */
649
650
651 T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number; /* channel parameter */
652 T_DMA_TYPE_CHANNEL_SECURED d_dma_channel_secured;
653 T_DMA_TYPE_CHANNEL_DATA_TYPE d_dma_channel_data_type; /* type of element to be transfered */
654
655 T_DMA_TYPE_CHANNEL_PORT d_dma_channel_src_port; /* source port parameter */
656 T_DMA_TYPE_CHANNEL_PACKED d_dma_src_channel_packed;
657 T_DMA_TYPE_CHANNEL_BURST_EN d_dma_src_channel_burst_en;
658
659 T_DMA_TYPE_CHANNEL_PORT d_dma_channel_dst_port; /* destination port parameter */
660 T_DMA_TYPE_CHANNEL_PACKED d_dma_dst_channel_packed;
661 T_DMA_TYPE_CHANNEL_BURST_EN d_dma_dst_channel_burst_en;
662
663 T_DMA_TYPE_CHANNEL_HW_SYNCH d_dma_channel_hw_synch; /* channel parameter */
664 T_DMA_TYPE_CHANNEL_PRIORITY d_dma_channel_priority;
665 T_DMA_TYPE_CHANNEL_AUTO_INIT d_dma_channel_auto_init;
666 T_DMA_TYPE_CHANNEL_FIFO_FLUSH d_dma_channel_fifo_flush;
667
668 T_DMA_TYPE_CHANNEL_ADDR_MODE d_dma_src_channel_addr_mode; /* source addressing mode */
669 T_DMA_TYPE_CHANNEL_ADDR_MODE d_dma_dst_channel_addr_mode; /* destination addressinf mode */
670
671 T_DMA_TYPE_CHANNEL_IT_TIME_OUT d_dma_channel_it_time_out; /* channel interrupt setting */
672 T_DMA_TYPE_CHANNEL_IT_DROP d_dma_channel_it_drop;
673 T_DMA_TYPE_CHANNEL_IT_FRAME d_dma_channel_it_frame;
674 T_DMA_TYPE_CHANNEL_IT_BLOCK d_dma_channel_it_block;
675 T_DMA_TYPE_CHANNEL_IT_HALF_BLOCK d_dma_channel_it_half_block;
676
677 SYS_UWORD32 d_dma_channel_src_address; /* source address */
678 SYS_UWORD32 d_dma_channel_dst_address; /* destination address */
679
680 SYS_UWORD16 d_dma_channel_element_number; /* number of element per frame */
681 SYS_UWORD16 d_dma_channel_frame_number; /* number of frame to be transfered */
682 }
683 T_DMA_TYPE_CHANNEL_PARAMETER;
684
685
686
687
688 /****************************************************************************
689 * PROTOTYPE DEFINITION
690 ***************************************************************************/
691
692 SYS_UWORD16 f_dma_get_version_driver(void);
693
694
695
696 void f_dma_global_parameter_set(T_DMA_TYPE_GLOBAL_PARAMETER *p_dma_global_parameter);
697
698
699
700 void f_dma_channel_allocation_set(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number, T_DMA_TYPE_CHANNEL_ALLOCATION d_dma_channel_allocation);
701
702
703
704 void f_dma_channel_parameter_set(T_DMA_TYPE_CHANNEL_PARAMETER *p_dma_channel_parameter);
705
706
707
708 void f_dma_channel_enable (T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number);
709
710
711
712 void f_dma_channel_disable(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number);
713
714
715
716 void f_dma_channel_auto_init_disable(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number);
717
718
719 SYS_UWORD16 f_dma_get_channel_counter(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number);
720
721
722
723 void f_dma_channel_soft_reset(T_DMA_TYPE_CHANNEL_NUMBER d_dma_channel_number);
724
725
726 void f_dma_default_call_back_it(SYS_UWORD16 d_dma_channel_it_status);
727
728
729 void f_dma_interrupt_manager();
730
731 void f_dma_secure_interrupt_manager();
732
733 #endif /* (CHIPSET == 12) */
734
735 #endif /* __SYS_DMA_H__ */