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comparison chipsetsw/drivers/drv_core/inth/sys_inth32.c @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /* @(#) nom : sys_inth32.c SID: 1.2 date : 05/23/03 */
2 /* Filename: sys_inth32.c */
3 /* Version: 1.2 */
4 /******************************************************************************
5 * WIRELESS COMMUNICATION SYSTEM DEVELOPMENT
6 *
7 * (C) 2002 Texas Instruments France. All rights reserved
8 *
9 * Author : Francois AMAND
10 *
11 *
12 * Important Note
13 * --------------
14 *
15 * This S/W is a preliminary version. It contains information on a product
16 * under development and is issued for evaluation purposes only. Features
17 * characteristics, data and other information are subject to change.
18 *
19 * The S/W is furnished under Non Disclosure Agreement and may be used or
20 * copied only in accordance with the terms of the agreement. It is an offence
21 * to copy the software in any way except as specifically set out in the
22 * agreement. No part of this document may be reproduced or transmitted in any
23 * form or by any means, electronic or mechanical, including photocopying and
24 * recording, for any purpose without the express written permission of Texas
25 * Instruments Inc.
26 *
27 ******************************************************************************
28 *
29 * FILE NAME: sys_inth32.c
30 *
31 *
32 * PURPOSE: Interrupt Handler driver compiled in 32-bits mode.
33 *
34 *
35 * FILE REFERENCES:
36 *
37 * Name IO Description
38 * ------------- -- ---------------------------------------------
39 *
40 *
41 *
42 * EXTERNAL VARIABLES:
43 *
44 * Source:
45 *
46 * Name Type IO Description
47 * ------------- --------------- -- ------------------------------
48 *
49 *
50 *
51 * EXTERNAL REFERENCES:
52 *
53 * Name Description
54 * ------------------ -------------------------------------------------------
55 *
56 *
57 *
58 * ABNORMAL TERMINATION CONDITIONS, ERROR AND WARNING MESSAGES:
59 *
60 *
61 *
62 * ASSUMPTION, CONSTRAINTS, RESTRICTIONS:
63 *
64 *
65 *
66 * NOTES:
67 *
68 *
69 *
70 * REQUIREMENTS/FUNCTIONAL SPECIFICATION REFERENCES:
71 *
72 *
73 *
74 *
75 * DEVELOPMENT HISTORY:
76 *
77 * Date Name(s) Version Description
78 * ----------- -------------- ------- -------------------------------------
79 * 11-Oct-2002 Francois AMAND 0.0.1 First implementation
80 *
81 * ALGORITHM:
82 *
83 *
84 *****************************************************************************/
85
86 #include "l1sw.cfg"
87 #include "chipset.cfg"
88
89 #if (CHIPSET == 12)
90 #if (OP_L1_STANDALONE == 0)
91 #include "main/sys_types.h"
92 #else
93 #include "sys_types.h"
94 #endif
95 #include "sys_map.h"
96 #include "sys_inth.h"
97
98 /* GLOBAL CONSTANT VARIABLES:
99 *
100 * Variables Type Description
101 * --------------- ------- -----------------------------------------------
102 *
103 */
104 void f_inth_dummy(void);
105
106
107 /* GLOBAL CONSTANT VARIABLES:
108 *
109 * Variables Type Description
110 * --------------- ------- -----------------------------------------------
111 *
112 */
113
114
115
116
117 /* GLOBAL VARIABLES:
118 *
119 * Variables Type Description
120 * -------------------- ----------- --------------------------------------
121 * a_inth_it_handlers SYS_FUNC ** Indirect function address for IRQ and
122 * FIQ on main interrupt handler.
123 * a_inth2_irq_handlers SYS_FUNC * Indirect function address for IRQ on
124 * 2nd level interrupt handler.
125 * d_inth_dummy SYS_UWORD32 Count the number of unwanted interrupts
126 */
127
128 SYS_FUNC a_inth_it_handlers[C_INTH_NUM_INT][2] =
129 { // IRQ FIQ
130 { f_inth_dummy, f_inth_dummy }, // 0 : WATCHDOG TIMER
131 { f_inth_dummy, f_inth_dummy }, // 1 : TIMER 1
132 { f_inth_dummy, f_inth_dummy }, // 2 : TIMER 2
133 { f_inth_dummy, f_inth_dummy }, // 3 : TSP RECEIVE
134 { f_inth_dummy, f_inth_dummy }, // 4 : TPU FRAME
135 { f_inth_dummy, f_inth_dummy }, // 5 : TPU PAGE
136 { f_inth_dummy, f_inth_dummy }, // 6 : SIM
137 { f_inth_dummy, f_inth_dummy }, // 7 : UART_MODEM1
138 { f_inth_dummy, f_inth_dummy }, // 8 : KEYBOARD
139 { f_inth_dummy, f_inth_dummy }, // 9 : RTC_TIMER
140 { f_inth_dummy, f_inth_dummy }, // 10 : RTC_ALARM
141 { f_inth_dummy, f_inth_dummy }, // 11 : ULPD_GAUGING
142 { f_inth_dummy, f_inth_dummy }, // 12 : ABB_IRQ
143 { f_inth_dummy, f_inth_dummy }, // 13 : SPI
144 { f_inth_dummy, f_inth_dummy }, // 14 : DMA
145 { f_inth_dummy, f_inth_dummy }, // 15 : API
146 { f_inth_dummy, f_inth_dummy }, // 16 : GPIO
147 { f_inth_dummy, f_inth_dummy }, // 17 : ABB_FIQ
148 { f_inth_dummy, f_inth_dummy }, // 18 : UART_IRDA
149 { f_inth_dummy, f_inth_dummy }, // 19 : ULPD GSM TIMER
150 { f_inth_dummy, f_inth_dummy }, // 20 : GEA
151 { f_inth_dummy, f_inth_dummy }, // 21 : EXTERNAL IRQ 1
152 { f_inth_dummy, f_inth_dummy }, // 22 : EXTERNAL IRQ 2
153 { f_inth_dummy, f_inth_dummy }, // 23 : USIM Card Detect
154 { f_inth_dummy, f_inth_dummy }, // 24 : USIM
155 { f_inth_dummy, f_inth_dummy }, // 25 : LCD
156 { f_inth_dummy, f_inth_dummy }, // 26 : USB
157 { f_inth_dummy, f_inth_dummy }, // 27 : MMC/SD/MS
158 { f_inth_dummy, f_inth_dummy }, // 28 : UART_MODEM2
159 { f_inth_2nd_level_handler, f_inth_dummy }, // 29 : 2nd Interrupt Handler
160 { f_inth_dummy, f_inth_dummy }, // 30 : I2C
161 { f_inth_dummy, f_inth_dummy } // 31 : NAND FLASH
162 };
163
164 SYS_FUNC a_inth2_irq_handlers[C_INTH_2ND_NUM_INT] =
165 {
166 f_inth_dummy, // 0 : RNG
167 f_inth_dummy, // 1 : SHA1/MD5
168 f_inth_dummy, // 2 : EMPU
169 f_inth_dummy, // 3 : Secure DMA
170 f_inth_dummy // 4 : Secure TIMER
171 };
172
173 SYS_UWORD32 d_inth_dummy = 0L;
174
175
176 /******************************************************************************
177 *
178 * FUNCTION NAME: f_inth_dummy
179 * Handle dummy interrupts. Call of this function should never occurs
180 *
181 *
182 * ARGUMENT LIST:
183 *
184 * Argument Type IO Description
185 * ------------ ------------------- -- ---------------------------------
186 * chip-select.
187 *
188 * RETURN VALUE: None
189 *
190 *****************************************************************************/
191
192 void f_inth_dummy(void) {
193 d_inth_dummy++;
194 } /* f_inth_dummy() */
195
196
197
198 /******************************************************************************
199 *
200 * FUNCTION NAME: f_inth_irq_handler
201 * Entry point of ARM IRQ sub-routine.
202 *
203 *
204 * ARGUMENT LIST:
205 *
206 * Argument Type IO Description
207 * ------------ ------------------- -- ---------------------------------
208 *
209 * RETURN VALUE: None
210 *
211 *****************************************************************************/
212
213 void f_inth_irq_handler(void) {
214
215 a_inth_it_handlers[F_INTH_GET_IRQ][C_INTH_IRQ](); /* ACK IT */
216 F_INTH_VALID_NEXT(C_INTH_IRQ); /* valid next IRQ */
217
218 } /* f_inth_irq_handler() */
219
220
221
222 /******************************************************************************
223 *
224 * FUNCTION NAME: f_inth_fiq_handler
225 * Entry point of ARM FIQ sub-routine.
226 *
227 *
228 * ARGUMENT LIST:
229 *
230 * Argument Type IO Description
231 * ------------ ------------------- -- ---------------------------------
232 *
233 * RETURN VALUE: None
234 *
235 *****************************************************************************/
236
237 void f_inth_fiq_handler(void) {
238
239 a_inth_it_handlers[F_INTH_GET_FIQ][C_INTH_FIQ](); /* ACK IT */
240 F_INTH_VALID_NEXT(C_INTH_FIQ); /* valid next FIQ */
241
242 } /* f_inth_fiq_handler() */
243
244
245
246 /******************************************************************************
247 *
248 * FUNCTION NAME: f_inth_2nd_level_handler
249 * Sub-routine to manage 2nd level interrupt handler.
250 *
251 *
252 * ARGUMENT LIST:
253 *
254 * Argument Type IO Description
255 * ------------ ------------------- -- ---------------------------------
256 *
257 * RETURN VALUE: None
258 *
259 *****************************************************************************/
260
261 void f_inth_2nd_level_handler(void) {
262
263 a_inth2_irq_handlers[F_INTH2_GET_IRQ](); /* ACK IT */
264 F_INTH2_VALID_NEXT(C_INTH_IRQ); /* Valid next IRQ */
265
266 } /* f_inth_2nd_level_handler() */
267
268
269 #endif /* (CHIPSET == 12) */