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comparison chipsetsw/drivers/drv_core/rhea/rhea_arm.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : rhea_arm.h
12
13 Description : Header file for the ARM RHEA interface
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.5
20
21 Date and time : 01/30/01 10:22:28
22
23 Previous delta : 12/08/00 11:38:10
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.rhea_arm.h
26
27 Sccs Id (SID) : '@(#) rhea_arm.h 1.5 01/30/01 10:22:28 '
28
29
30 *****************************************************************************/
31
32 #include "chipset.cfg"
33
34 /**** RHEA control register ****/
35
36 #define RHEA_CNTL_FACT_0 0x000f /* Division factor for strobe 0 */
37 #define RHEA_CNTL_FACT_1 0x00f0 /* Division factor for strobe 1 */
38 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
39 #define RHEA_CNTL_TIMEOUT 0xff00 /* RHEA bus access timeout */
40 #else
41 #define RHEA_CNTL_TIMEOUT 0xfe00 /* RHEA bus access timeout */
42 #endif
43
44 /**** API control register ****/
45
46 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
47 #define RHEA_API_WS_H 0x001f /* API wait states when DSP is in HOM mode */
48 #define RHEA_API_WS_S 0x03e0 /* API wait states when DSP in in SAM mode */
49 #else
50 #define RHEA_API_WS_H 0x001f /* API wait states for High clkout */
51 #define RHEA_API_WS_L 0x02e0 /* API wait states for Low clkout */
52 #endif
53
54 /**** ARM RHEA control register ****/
55
56 #define RHEA_ARM_WEN_0 0x0001 /* Write enable for strobe 0 */
57 #define RHEA_ARM_WEN_1 0x0002 /* Write enable for strobe 1 */
58
59 /*--------------------------------------------------------------
60 * RHEA_INITRHEA()
61 *--------------------------------------------------------------
62 * Parameters :Fac0 acces factor strb0, Fac1 acces factor strb1
63 * timeout max time periph stall the processor
64 * Return : none
65 * Functionality :Initialize the RHEA control register
66 *--------------------------------------------------------------*/
67
68 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
69 #define RHEA_INITRHEA(Fac0,Fac1,TimeOut) (* (unsigned short *) MEM_RHEA_CNTL = (Fac0 | Fac1 << 4 | TimeOut << 8))
70 #else
71 #define RHEA_INITRHEA(Fac0,Fac1,TimeOut) (* (unsigned short *) MEM_RHEA_CNTL = (Fac0 | Fac1 << 4 | TimeOut << 9))
72 #endif
73
74 /*--------------------------------------------------------------
75 * RHEA_INITAPI()
76 *--------------------------------------------------------------
77 * Parameters :wsH wait states when freq high, wsL wait states
78 * when freq low
79 * Return : none
80 * Functionality :Initialize the API control register
81 *--------------------------------------------------------------*/
82
83 #define RHEA_INITAPI(wsH, wsL) (* (SYS_UWORD16 *) MEM_API_CNTL = ((wsH) | (wsL) << 5))
84
85 /*--------------------------------------------------------------
86 * RHEA_INITARM()
87 *--------------------------------------------------------------
88 * Parameters : Wen0 write enable domain strb0
89 * Wen1 write enable domain strb1
90 * Return : none
91 * Functionality :Initialize the ARM RHEA control register
92 *--------------------------------------------------------------*/
93
94 #define RHEA_INITARM(Wen0,Wen1) (* (SYS_UWORD16 *) MEM_ARM_RHEA = ((Wen0) | (Wen1) << 1))