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comparison chipsetsw/layer1/cust0/l1_rf12.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename l1_rf12.h
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8
9 #ifndef __L1_RF_H__
10 #define __L1_RF_H__
11
12 #define RF_RITA_10 0x2030 // Check with TIDK
13
14 //#define RF_HW_BAND_EGSM
15 //#define RF_HW_BAND_DCS
16 #define RF_HW_BAND_PCS 0x4
17 #define RF_HW_BAND_DUAL_US 0x80
18 #define RF_HW_BAND_DUAL_EXT 0x20
19
20 //#define RF_HW_BAND_SUPPORT (0x0020 | RF_HW_BAND_PCS) // radio_band_support E-GSM/DCS + PCS
21 // radio_band_support E-GSM/DCS + GSM850/PCS
22 #define RF_HW_BAND_SUPPORT (RF_HW_BAND_DUAL_EXT | RF_HW_BAND_DUAL_US)
23
24 // L1 RF SW Multiband configuration
25 //--------------------------
26
27 // RF_SW_MULTIBAND_SUPPORT values
28 #define SINGLE_BAND_900 1
29 #define SINGLE_BAND_1800 2
30 #define SINGLE_BAND_850 3
31 #define SINGLE_BAND_1900 4
32 #define DUAL_BAND_900_1800 5
33 #define DUAL_BAND_850_1900 6
34 #define TRI_BAND_900_1800_1900 7
35 #define TRI_BAND_850_1900_1800 8
36 #define QUAD_BAND 9
37
38 //IMPORTANT !: To change RF_SW_MULTIBAND_SUPPORT value, it must be synchronized with other multiband settings in the software
39 // To match the protocol stack settings( e.g EF_RFCAP ) in order to make sure that the value of STD sent in MPHC_INIT_L1_REQ is supported by L1
40 // And also match the RF HW support: RF_HW_BAND_SUPPORT
41 #define RF_SW_MULTIBAND_SUPPORT QUAD_BAND
42
43 // Generate band dependancy options
44 #define RF_SW_BAND900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
45 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND) )
46
47 #define RF_SW_BAND1800 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1800) ||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_900_1800) \
48 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900) ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
49 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
50
51 #define RF_SW_BAND850 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_850)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
52 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
53
54 #define RF_SW_BAND1900 ((RF_SW_MULTIBAND_SUPPORT == SINGLE_BAND_1900)||(RF_SW_MULTIBAND_SUPPORT == DUAL_BAND_850_1900) \
55 ||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_900_1800_1900)||(RF_SW_MULTIBAND_SUPPORT == TRI_BAND_850_1900_1800) \
56 ||(RF_SW_MULTIBAND_SUPPORT == QUAD_BAND))
57
58 /************************************/
59 /* SYNTHESIZER setup time... */
60 /************************************/
61 #define RX_SYNTH_SETUP_TIME (PROVISION_TIME - TRF_R1)//RX Synthesizer setup time in qbit.
62 #define TX_SYNTH_SETUP_TIME (- TRF_T1) //TX Synthesizer setup time in qbit.
63
64 /************************************/
65 /* time for TPU scenario ending... */
66 /************************************/
67 //
68 // The following values are used to take into account any TPU activity AFTER
69 // BDLON (or BDLENA) down (for RX) and BULON down (for TX)
70 // - If there are no TPU commands after BDLON (or BDLENA) down and BULON down,
71 // these defines must be ZERO
72 // - If there IS some TPU command after BDLON (or BDLENA) and BULON down,
73 // these defines must be equal to the time difference (in qbits) between
74 // the BDLON (or BDLENA) or BULON time and the last TPU command on
75 // the TPU scenario
76 #define RX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BDLENA down
77 #define TX_TPU_SCENARIO_ENDING 0 // execution time of AFTER BULON down
78
79
80 /******************************************************/
81 /* TXPWR configuration... */
82 /* Fixed TXPWR value when GSM management is disabled. */
83 /******************************************************/
84
85 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
86 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
87 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
88 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
89 #endif
90
91
92 /************************************/
93 /* ANALOG delay (in qbits) */
94 /************************************/
95 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
96 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block
97 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
98 #if (ANLG_FAM == 1)
99 #define UL_ABB_DELAY 3 // modulator input to output delay
100 #endif
101 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
102 #define UL_ABB_DELAY 3 // modulator input to output delay
103 #endif
104
105 /************************************/
106 /* TX Propagation delay... */
107 /************************************/
108 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
109 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
110 #endif
111
112 /************************************/
113 /* Initial value for APC DELAY */
114 /************************************/
115 #if (ANLG_FAM == 1)
116 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
117 #define APCDEL_DOWN 2 // minimum value: 2
118 #define APCDEL_UP (6+5) // minimum value: 6
119 #endif
120
121 #if (ANLG_FAM == 2) || (ANLG_FAM == 3)
122 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
123 #define APCDEL_DOWN (2+0) // minimum value: 2
124 #define APCDEL_UP (6+3+1) // minimum value: 6
125 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8)
126 #endif
127
128 #define GUARD_BITS 7
129
130 /************************************/
131 /* Initial value for AFC... */
132 /************************************/
133 #define EEPROM_AFC ((150)*8) // F13.3 required!!!!! (default : -952*8, initial deviation of -2400 forced)
134
135 #define SETUP_AFC_AND_RF 6 // AFC converges in 2 frames and RF BAND GAP stable after 4 frames
136 // Rita (RF=12) LDO wakeup requires 6 frames
137
138 /************************************/
139 /* Baseband registers */
140 /************************************/
141 #if (ANLG_FAM == 1)
142 // Omega registers values will be programmed at 1st DSP communication interrupt
143 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
145 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute
146 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB
147 // RITA does not need an APCOFFSET because the PACTRL is internal:
148 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // value at reset-Changed from 0x0016- CR 27.12
149 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE)
150 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
151 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
152 #define C_DAI_ON_OFF (0x000) // value at reset
153 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
154 #define C_VBCTRL ((0x00B << 6) | VBCTRL | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
155 // BULRUDEL will be initialized on rach only ....
156 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
157 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
158 #endif
159
160 #if (ANLG_FAM == 2)
161
162 // IOTA registers values will be programmed at 1st DSP communication interrupt
163
164 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
165 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
166 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3 dB, Sidetone gain to -17dB
167 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
168 // RITA does not need an APCOFFSET because the PACTRL is internal:
169 // REMOVE //#define C_APCOFF 0x1016 | (0x3c << 6) | TRUE // x2 slope 128
170 #if (RF_PA == 0 || RF_PA == 3)
171 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
172 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
173 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
174 #endif
175 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
176 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
177 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
178 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
179
180
181 // audio patch for H2-sample:
182 #if (RAZ_VULSWITCH_REGAUDIO == 1)
183 #define C_VBCTRL1 ((0x003 << 6) | VBCTRL1 | TRUE) // VBDFAUXG = 1, VULSWITCH=0, VDLAUX=1, VDLEAR=1 // jkb h2sample change
184 #else
185 #define C_VBCTRL1 ((0x00B << 6) | VBCTRL1 | TRUE) // VULSWITCH=1, VDLAUX=1, VDLEAR=1
186 #endif
187
188
189 #define C_VBCTRL2 ((0x000 << 6) | VBCTRL2 | TRUE) // MICBIASEL=0, VDLHSO=0, MICAUX=0
190 // BULRUDEL will be initialized on rach only ....
191 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
192 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
193 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
194 // Monoslot, Vpp=8/15*Vref
195 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
196 #endif
197
198 #if (ANLG_FAM == 3)
199
200 // SYREN registers values will be programmed at 1st DSP communication interrupt
201
202 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
203 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
204 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE) // Uplink gain amp 3dB, Sidetone gain to -17 dB
205 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control -12 dB
206 #if (RF_PA == 0 || RF_PA == 3)
207 #define C_APCOFF ((0x040 << 6) | APCOFF | TRUE) // x2 slope 128
208 #elif (RF_PA == 1 || RF_PA == 2 || RF_PA == 4)
209 #define C_APCOFF ((0x070 << 6) | APCOFF | TRUE) // x2 slope 128
210 #endif
211 #define C_BULIOFF ((0x0FF << 6) | BULIOFF | TRUE) // value at reset
212 #define C_BULQOFF ((0x0FF << 6) | BULQOFF | TRUE) // value at reset
213 #define C_DAI_ON_OFF ((0x000 << 6) | APCOFF | TRUE) // value at reset
214 #define C_AUXDAC ((0x000 << 6) | AUXDAC | TRUE) // value at reset
215 #define C_VBCTRL1 ((0x108 << 6) | VBCTRL1 | TRUE) // VULSWITCH=1 AUXI 28,2 dB
216 #define C_VBCTRL2 ((0x001 << 6) | VBCTRL2 | TRUE) // HSMIC on, SPKG gain @ 2,5dB
217
218 // BULRUDEL will be initialized on rach only ....
219 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6)<<6) | APCDEL1)
220 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE) //
221 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
222 // Monoslot, Vpp=8/15*Vref
223 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
224
225 #define C_VBPOP ((0x004 << 6) | VBPOP | TRUE) // HSOAUTO enabled only
226 #define C_VAUDINITD 2 // vaud_init_delay init 2 frames
227 #define C_VAUDCTRL ((0x000 << 6) | VAUDCTRL | TRUE) // Init to zero
228 #define C_VAUOCTRL ((0x155 << 6) | VAUOCTRL | TRUE) // Speech on all outputs
229 #define C_VAUSCTRL ((0x000 << 6) | VAUSCTRL | TRUE) // Init to zero
230 #define C_VAUDPLL ((0x000 << 6) | VAUDPLL | TRUE) // Init to zero
231
232 // SYREN registers values programmed by L1 directly through SPI (ABB_on)
233
234 #define C_BBCFG (0x44) // Syren Like BDLF Filter - DC OFFSET removal OFF
235
236 #endif
237
238
239 /************************************/
240 /* Automatic frequency compensation */
241 /************************************/
242 /********************* C_Psi_sta definition *****************************/
243 /* C_Psi_sta = (2*pi*Fr) / (N * Fb) */
244 /* (1) = (2*pi*V*ppm*0.9) / (N*V*Fb) */
245 /* regarding Vega V/N = 2.4/4096 */
246 /* regarding VCO ppm/V = 16 / 1 (average slope of the VCO) */
247 /* (1) = (2*pi*2.4*16*0.9) / (4096*1*270.83) */
248 /* = 0.000195748 */
249 /* C_Psi_sta_inv = 1/C_Psi_sta = 5108 */
250 /************************************************************************/
251
252 #define C_Psi_sta_inv 5419L // (1/C_Psi_sta)
253 #define C_Psi_st 10L // C_Psi_sta * 0.8 F0.16
254 #define C_Psi_st_32 634112L // F0.32
255 #define C_Psi_st_inv 6773L // (1/C_Psi_st)
256
257 #if (VCXO_ALGO == 1)
258 // Linearity parameters
259 #define C_AFC_DAC_CENTER ((111)*8)
260 #define C_AFC_DAC_MIN ((-1196)*8)
261 #define C_AFC_DAC_MAX ((1419)*8)
262
263 #define C_AFC_SNR_THR 2560 // 1/0.4 * 2**10
264 #endif
265
266 typedef struct
267 {
268 WORD16 eeprom_afc;
269 UWORD32 psi_sta_inv;
270 UWORD32 psi_st;
271 UWORD32 psi_st_32;
272 UWORD32 psi_st_inv;
273
274 #if (VCXO_ALGO)
275 // VCXO adjustment parameters
276 // Parameters used when assuming linearity
277 WORD16 dac_center;
278 WORD16 dac_min;
279 WORD16 dac_max;
280 WORD16 snr_thr;
281 #endif
282 }
283 T_AFC_PARAMS;
284
285 /************************************/
286 /* Swap IQ definitions... */
287 /************************************/
288 /* 0=No Swap, 1=Swap RX only, 2=Swap TX only, 3=Swap RX and TX */
289 #if (RF_PG == R_PG_10)
290 // PG 1.0 -> 1 (Swap RX only)
291 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
292 #define SWAP_IQ_GSM 1
293 #define SWAP_IQ_DCS 1
294 #define SWAP_IQ_PCS 1
295 #define SWAP_IQ_GSM850 3 // Swap TX compared to GSM 900
296 #else
297 // All PG versions ABOVE 1.0 -> 0 (No Swap)
298 // GSM 850 => TX is ALWAYS swapped compared to GSM 900
299 #define SWAP_IQ_GSM 0
300 #define SWAP_IQ_DCS 0
301 #define SWAP_IQ_PCS 0
302 #define SWAP_IQ_GSM850 2 // Swap TX compared to GSM 900
303 #endif
304
305 /************************************/
306 /************************************/
307 // typedef
308 /************************************/
309 /************************************/
310
311 /*************************************************************/
312 /* Define structure for apc of TX Power ******/
313 /*************************************************************/
314 typedef struct
315 { // pcm-file "rf/tx/level.gsm|dcs"
316 UWORD16 apc; // 0..31
317 UWORD8 ramp_index; // 0..RF_TX_RAMP_SIZE
318 UWORD8 chan_cal_index; // 0..RF_TX_CHAN_CAL_TABLE_SIZE
319 }
320 T_TX_LEVEL;
321
322 /************************************/
323 /* Automatic Gain Control */
324 /************************************/
325 /* Define structure for sub-band definition of TX Power ******/
326 typedef struct
327 {
328 UWORD16 upper_bound; //highest physical arfcn of the sub-band
329 WORD16 agc_calib; // AGC for each TXPWR
330 }T_RF_AGC_BAND;
331
332 /************************************/
333 /* Ramp definitions */
334 /************************************/
335 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
336 typedef struct
337 {
338 UWORD8 ramp_up [16]; // Ramp-up profile
339 UWORD8 ramp_down [16]; // Ramp-down profile
340 }
341 T_TX_RAMP;
342 #endif
343
344
345 // RF structure definition
346 //========================
347
348 // Number of bands supported
349 #define GSM_BANDS 2
350
351 #define MULTI_BAND1 0
352 #define MULTI_BAND2 1
353 // RF table sizes
354 #define RF_RX_CAL_CHAN_SIZE 10 // number of AGC sub-bands
355 #define RF_RX_CAL_TEMP_SIZE 11 // number of temperature ranges
356
357 #define RF_TX_CHAN_CAL_TABLE_SIZE 4 // channel calibration table size
358 #define RF_TX_NUM_SUB_BANDS 8 // number of sub-bands in channel calibration table
359 #define RF_TX_LEVELS_TABLE_SIZE 32 // level table size
360 #define RF_TX_RAMP_SIZE 16 // number of ramp definitions
361 #define RF_TX_CAL_TEMP_SIZE 5 // number of temperature ranges
362
363 #define AGC_TABLE_SIZE 20
364 #define MIN_AGC_INDEX 6
365
366 #define TEMP_TABLE_SIZE 131 // number of elements in ADC->temp conversion table
367
368
369 // RX parameters and tables
370 //-------------------------
371
372 // AGC parameters and tables
373 typedef struct
374 {
375 UWORD16 low_agc_noise_thr;
376 UWORD16 high_agc_sat_thr;
377 UWORD16 low_agc;
378 UWORD16 high_agc;
379 UWORD8 il2agc_pwr[121];
380 UWORD8 il2agc_max[121];
381 UWORD8 il2agc_av[121];
382 }
383 T_AGC;
384
385 // Calibration parameters
386 typedef struct
387 {
388 UWORD16 g_magic;
389 UWORD16 lna_att;
390 UWORD16 lna_switch_thr_low;
391 UWORD16 lna_switch_thr_high;
392 }
393 T_RX_CAL_PARAMS;
394
395 // RX temperature compensation
396 typedef struct
397 {
398 WORD16 temperature;
399 WORD16 agc_calib;
400 }
401 T_RX_TEMP_COMP;
402
403 // RF RX structure
404 typedef struct
405 {
406 T_AGC agc;
407 }
408 T_RF_RX; //common
409
410 // RF RX structure
411 typedef struct
412 {
413 T_RX_CAL_PARAMS rx_cal_params;
414 T_RF_AGC_BAND agc_bands[RF_RX_CAL_CHAN_SIZE];
415 T_RX_TEMP_COMP temp[RF_RX_CAL_TEMP_SIZE];
416 }
417 T_RF_RX_BAND;
418
419
420 // TX parameters and tables
421 //-------------------------
422
423 // TX temperature compensation
424 typedef struct
425 {
426 WORD16 temperature;
427 #if (ORDER2_TX_TEMP_CAL==1)
428 WORD16 a;
429 WORD16 b;
430 WORD16 c;
431 #else
432 WORD16 apc_calib;
433 #endif
434 }
435 T_TX_TEMP_CAL;
436
437 // Ramp up and ramp down delay
438 typedef struct
439 {
440 UWORD16 up;
441 UWORD16 down;
442 }
443 T_RAMP_DELAY;
444
445 typedef struct
446 {
447 UWORD16 arfcn_limit;
448 WORD16 chan_cal;
449 }
450 T_TX_CHAN_CAL;
451
452 // RF TX structure
453 typedef struct
454 {
455 T_RAMP_DELAY ramp_delay;
456 UWORD8 guard_bits; // number of guard bits needed for ramp up
457 UWORD8 prg_tx;
458 }
459 T_RF_TX; //common
460
461 // RF TX structure
462 typedef struct
463 {
464 T_TX_LEVEL levels[RF_TX_LEVELS_TABLE_SIZE];
465 T_TX_CHAN_CAL chan_cal_table[RF_TX_CHAN_CAL_TABLE_SIZE][RF_TX_NUM_SUB_BANDS];
466 T_TX_RAMP ramp_tables[RF_TX_RAMP_SIZE];
467 T_TX_TEMP_CAL temp[RF_TX_CAL_TEMP_SIZE];
468 }
469 T_RF_TX_BAND;
470
471 // band structure
472 typedef struct
473 {
474 T_RF_RX_BAND rx;
475 T_RF_TX_BAND tx;
476 UWORD8 swap_iq;
477 }
478 T_RF_BAND;
479
480 // RF structure
481 typedef struct
482 {
483 // common for all bands
484 UWORD16 rf_revision;
485 UWORD16 radio_band_support;
486 T_RF_RX rx;
487 T_RF_TX tx;
488 T_AFC_PARAMS afc;
489 }
490 T_RF;
491
492 /************************************/
493 /* MADC definitions */
494 /************************************/
495 // Omega: 5 external channels if touch screen not used, 3 otherwise
496 enum ADC_INDEX {
497 ADC_VBAT,
498 ADC_VCHARG,
499 ADC_ICHARG,
500 ADC_VBACKUP,
501 ADC_BATTYP,
502 ADC_BATTEMP,
503 ADC_ADC3, // name of this ??
504 ADC_RFTEMP,
505 ADC_ADC4,
506 ADC_INDEX_END // ADC_INDEX_END must be the end of the enums
507 };
508
509 typedef struct
510 {
511 WORD16 converted[ADC_INDEX_END]; // converted
512 UWORD16 raw[ADC_INDEX_END]; // raw from ADC
513 }
514 T_ADC;
515
516 /************************************/
517 /* MADC calibration */
518 /************************************/
519 typedef struct
520 {
521 UWORD16 a[ADC_INDEX_END];
522 WORD16 b[ADC_INDEX_END];
523 }
524 T_ADCCAL;
525
526 // Conversion table: ADC value -> temperature
527 typedef struct
528 {
529 UWORD16 adc; // ADC reading is 10 bits
530 WORD16 temp; // temp is in approx. range -30..+80
531 }
532 T_TEMP;
533
534 typedef struct
535 {
536 char *name;
537 void *addr;
538 int size;
539 }
540 T_CONFIG_FILE;
541
542 typedef struct
543 {
544 char *name; // name of ffs file suffix
545 T_RF_BAND *addr; // address to default flash structure
546 UWORD16 max_carrier; // max carrier
547 UWORD16 max_txpwr; // max tx power
548 }
549 T_BAND_CONFIG;
550
551 typedef struct
552 {
553 UWORD8 band[GSM_BANDS]; // index to band address
554 UWORD8 txpwr_tp; // tx power turning point
555 UWORD16 first_arfcn; // first index
556 }
557 T_STD_CONFIG;
558 enum GSMBAND_DEF
559 {
560 BAND_NONE,
561 BAND_EGSM900,
562 BAND_DCS1800,
563 BAND_PCS1900,
564 BAND_GSM850,
565 // put new bands here
566 BAND_GSM900 //last entry
567 };
568
569 /************************************/
570 /* ABB (Omega) Initialization */
571 /************************************/
572
573 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
574 #define ABB_TABLE_SIZE 16
575 #elif (ANLG_FAM == 3)
576 #define ABB_TABLE_SIZE 22
577 #endif
578
579 // Note that this translation is probably not needed at all. But until L1 is
580 // (maybe) changed to simply initialize the ABB from a table of words, we
581 // use this to make things more easy-readable.
582
583 #if (ANLG_FAM == 1)
584 enum ABB_REGISTERS {
585 ABB_AFCCTLADD = 0,
586 ABB_VBUCTRL,
587 ABB_VBDCTRL,
588 ABB_BBCTRL,
589 ABB_APCOFF,
590 ABB_BULIOFF,
591 ABB_BULQOFF,
592 ABB_DAI_ON_OFF,
593 ABB_AUXDAC,
594 ABB_VBCTRL,
595 ABB_APCDEL1
596 };
597 #elif (ANLG_FAM == 2)
598 enum ABB_REGISTERS {
599 ABB_AFCCTLADD = 0,
600 ABB_VBUCTRL,
601 ABB_VBDCTRL,
602 ABB_BBCTRL,
603 ABB_BULGCAL,
604 ABB_APCOFF,
605 ABB_BULIOFF,
606 ABB_BULQOFF,
607 ABB_DAI_ON_OFF,
608 ABB_AUXDAC,
609 ABB_VBCTRL1,
610 ABB_VBCTRL2,
611 ABB_APCDEL1,
612 ABB_APCDEL2
613 };
614 #elif (ANLG_FAM == 3)
615 enum ABB_REGISTERS {
616 ABB_AFCCTLADD = 0,
617 ABB_VBUCTRL,
618 ABB_VBDCTRL,
619 ABB_BBCTRL,
620 ABB_BULGCAL,
621 ABB_APCOFF,
622 ABB_BULIOFF,
623 ABB_BULQOFF,
624 ABB_DAI_ON_OFF,
625 ABB_AUXDAC,
626 ABB_VBCTRL1,
627 ABB_VBCTRL2,
628 ABB_APCDEL1,
629 ABB_APCDEL2,
630 ABB_VBPOP,
631 ABB_VAUDINITD,
632 ABB_VAUDCTRL,
633 ABB_VAUOCTRL,
634 ABB_VAUSCTRL,
635 ABB_VAUDPLL
636 };
637 #endif
638 #endif