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comparison chipsetsw/layer1/tm_include/l1tm_msgty.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1TM_MSGTY.H
4 *
5 * Filename l1tm_msgty.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10
11 /***********************************************************************/
12 /* TESTMODE 3.X */
13 /***********************************************************************/
14
15
16 typedef struct
17 {
18 UWORD8 cid;
19 UWORD8 str_len_in_bytes;
20
21 // all primitive types should be a unique struct within
22 // the union u.
23 union
24 {
25 struct
26 {
27 WORD16 index;
28 UWORD16 value;
29 } tm_params;
30 struct
31 {
32 WORD8 index;
33 UWORD8 table[TM_PAYLOAD_UPLINK_SIZE_MAX];
34 } tm_table;
35 struct
36 {
37 UWORD32 address;
38 UWORD8 table[TM_PAYLOAD_UPLINK_SIZE_MAX];
39 } mem_write;
40 struct
41 {
42 UWORD32 src;
43 UWORD32 length;
44 } mem_read;
45 struct
46 {
47 UWORD8 packet[128];
48 } ffs;
49 } u;
50 }
51 T_TESTMODE_PRIM;
52
53 typedef struct
54 {
55 UWORD32 arfcn;
56 UWORD32 number_of_measurements;
57 UWORD8 place_of_measurement;
58 UWORD32 num_loop;
59 UWORD32 agc;
60 }
61 T_TMODE_PM_REQ;
62
63 typedef struct
64 {
65 UWORD16 power_array_size;
66 T_POWER_ARRAY power_array[1];
67 }
68 T_TMODE_RXLEV_REQ;
69
70 typedef struct
71 {
72 UWORD32 dummy;
73 }
74 T_TMODE_FB0_REQ;
75
76 typedef struct
77 {
78 UWORD32 dummy;
79 }
80 T_TMODE_FB1_REQ;
81
82 typedef struct
83 {
84 UWORD32 dummy;
85 }
86 T_TMODE_SB_REQ;
87
88 typedef struct
89 {
90 UWORD32 dummy;
91 }
92 T_TMODE_FB_SB_REQ;
93
94 typedef struct
95 {
96 BOOL fb_flag; //TRUE if FB found, otherwise FALSE
97 WORD8 ntdma; //tdma between window start and beginning of FB (0..23)
98 UWORD8 neigh_id;
99 UWORD32 pm_fullres;
100 UWORD32 toa;
101 WORD16 angle;
102 UWORD32 snr;
103 }
104 T_TMODE_FB_CON;
105
106 typedef struct
107 {
108 UWORD16 radio_freq;
109 BOOL sb_flag;
110 UWORD32 fn_offset;
111 UWORD32 time_alignmt;
112 UWORD8 bsic;
113 UWORD8 neigh_id;
114 UWORD8 attempt;
115 UWORD32 pm_fullres;
116 UWORD32 toa;
117 WORD16 angle;
118 UWORD32 snr;
119 }
120 T_TMODE_NCELL_SYNC_IND;
121
122 typedef struct
123 {
124 UWORD32 fn_offset;
125 UWORD32 time_alignmt;
126 UWORD8 bsic;
127 }
128 T_TMODE_NEW_SCELL_REQ;
129
130 typedef struct
131 {
132 UWORD16 radio_freq;
133 UWORD8 l2_channel;
134 BOOL error_flag;
135 T_RADIO_FRAME l2_frame;
136 UWORD8 tc;
137 UWORD32 fn;
138 UWORD8 neigh_id;
139 }
140 T_TMODE_BCCHS_CON;
141
142 typedef struct
143 {
144 UWORD32 dummy;
145 }
146 T_TMODE_STOP_SCELL_BCCH_REQ;
147
148 typedef struct
149 {
150 UWORD32 dummy;
151 }
152 T_TMODE_SCELL_NBCCH_REQ;
153
154 typedef struct
155 {
156 UWORD32 fn;
157 UWORD8 channel_request;
158 }
159 T_TMODE_RA_DONE;
160
161 typedef struct
162 {
163 UWORD32 dummy;
164 }
165 T_TMODE_RA_START;
166
167 typedef struct
168 {
169 #if (CODE_VERSION == SIMULATION)
170 UWORD8 ul_dl;
171 #else
172 UWORD32 dummy;
173 #endif
174 }
175 T_TMODE_IMMED_ASSIGN_REQ;
176
177 typedef struct
178 {
179 UWORD8 A[22+1];
180 }
181 T_TMODE_RADIO_FRAME;
182
183 typedef struct
184 {
185 UWORD16 radio_freq;
186 UWORD8 l2_channel;
187 UWORD8 error_cause;
188 T_TMODE_RADIO_FRAME l2_frame;
189 UWORD8 bsic;
190 UWORD8 tc;
191 }
192 T_TMODE_SACCH_INFO;
193
194 typedef struct
195 {
196 UWORD32 pm_fullres;
197 UWORD32 snr;
198 UWORD32 toa;
199 WORD16 angle;
200 UWORD32 qual_nbr_meas_full; // Fullset: nbr meas. of rxqual.
201 UWORD32 qual_full; // Fullset: rxqual meas.
202 }
203 T_TMODE_TCH_INFO;
204
205 typedef struct
206 {
207 UWORD32 none;
208 }
209 T_TMODE_STOP_RX_TX;
210
211 #if L1_GPRS
212 typedef struct
213 {
214 #if (CODE_VERSION == SIMULATION)
215 UWORD8 multislot_class;
216 UWORD8 dl_ts_alloc;
217 UWORD8 ul_ts_alloc;
218 UWORD8 ul_alloc_length;
219 BOOL mon_enable;
220 BOOL pm_enable;
221 #else
222 UWORD32 dummy;
223 #endif
224 }
225 T_TMODE_PDTCH_ASSIGN_REQ;
226
227 typedef struct
228 {
229 UWORD32 pm_fullres;
230 UWORD32 snr;
231 UWORD32 toa;
232 WORD16 angle;
233 BOOL crc_error_tbl[8];
234 }
235 T_TMODE_PDTCH_INFO;
236 #endif
237
238
239
240 /**************** ENUMs ***********************/
241
242 // TestMode Error Codes
243 enum
244 {
245 E_OK = 0, // Function completed successfully.
246 E_FINISHED = 1, // Previously started operation has finished.
247 E_TESTMODE = 2, // Function not legal in this GGT test mode.
248 E_BADINDEX = 3, // The index is undefined.
249 E_INVAL = 4, // Invalid Argument (out of range or other).
250 E_BADSIZE = 7, // Some table or list parameter was wrong in size
251 E_AGAIN = 8, // Not ready, try again later.
252 E_NOSYS = 9, // Function not implemented.
253 E_NOSUBSYS = 10, // Sub-Function not implemented.
254 E_BADCID = 14, // Invalid CID.
255 E_CHECKSUM = 15, // Checksum Error.
256 E_PACKET = 16, // Packet format is bad (wrong number of arguments).
257 E_FORWARD = 31 // Command parsed successfully, but further processing necessary
258 };
259
260 // CID's
261 enum
262 {
263 TM_INIT = 0x20,
264 TM_MODE_SET = 0x21,
265 VERSION_GET = 0x22,
266 RF_ENABLE = 0x23,
267 STATS_READ = 0x24,
268 STATS_CONFIG_WRITE = 0x25,
269 STATS_CONFIG_READ = 0x26,
270 RF_PARAM_WRITE = 0x30,
271 RF_PARAM_READ = 0x31,
272 RF_TABLE_WRITE = 0x32,
273 RF_TABLE_READ = 0x33,
274 RX_PARAM_WRITE = 0x34,
275 RX_PARAM_READ = 0x35,
276 TX_PARAM_WRITE = 0x36,
277 TX_PARAM_READ = 0x37,
278 TX_TEMPLATE_WRITE = 0x38,
279 TX_TEMPLATE_READ = 0x39,
280 MEM_WRITE = 0x40,
281 MEM_READ = 0x41,
282 CODEC_WRITE = 0x42,
283 CODEC_READ = 0x43,
284 MISC_PARAM_WRITE = 0x44,
285 MISC_PARAM_READ = 0x45,
286 MISC_TABLE_WRITE = 0x46,
287 MISC_TABLE_READ = 0x47,
288 MISC_ENABLE = 0x48,
289 SPECIAL_PARAM_WRITE = 0x50,
290 SPECIAL_PARAM_READ = 0x51,
291 SPECIAL_TABLE_WRITE = 0x52,
292 SPECIAL_TABLE_READ = 0x53,
293 SPECIAL_ENABLE = 0x54,
294
295 #if (CODE_VERSION != SIMULATION)
296 TPU_TABLE_WRITE = 0x55,
297 TPU_TABLE_READ = 0x56,
298 #endif
299
300 TM_FFS = 0x70
301 };
302
303 // TestMode function enum's
304 enum RF_PARAM
305 {
306 BCCH_ARFCN = 1,
307 TCH_ARFCN = 2,
308 MON_ARFCN = 3,
309 #if L1_GPRS
310 PDTCH_ARFCN = 4,
311 #endif
312 STD_BAND_FLAG = 7,
313 AFC_ENA_FLAG = 8,
314 AFC_DAC_VALUE = 9,
315 INITIAL_AFC_DAC = 10
316 #if L1_GPRS
317 ,MULTISLOT_CLASS = 20
318 #endif
319 };
320
321 enum RF_TABLE
322 {
323 RX_AGC_TABLE = 8,
324 AFC_PARAMS = 9,
325 RX_AGC_GLOBAL_PARAMS = 12,
326 RX_IL_2_AGC_MAX = 13,
327 RX_IL_2_AGC_PWR = 14,
328 RX_IL_2_AGC_AV = 15,
329 TX_LEVELS = 16, // 16=GSM900, 32=DCS1800, 48=PCS1900
330 TX_CAL_CHAN = 17, // 17=GSM900, 33=DCS1800, 49=PCS1900
331
332 #if (ORDER2_TX_TEMP_CAL==1)
333 TX_CAL_TEMP = 20, // 20=GSM900, 36=DCS1800, 52=PCS1900
334 #else
335 TX_CAL_TEMP = 18, // 18=GSM900, 34=DCS1800, 50=PCS1900
336 #endif
337
338 TX_CAL_EXTREME = 19, // 19=GSM900, 35=DCS1800, 51=PCS1900
339 RX_CAL_CHAN = 25, // 25=GSM900, 41=DCS1800, 57=PCS1900
340 RX_CAL_TEMP = 26, // 26=GSM900, 42=DCS1800, 58=PCS1900
341 RX_CAL_LEVEL = 27, // 27=GSM900, 43=DCS1800, 59=PCS1900
342 RX_AGC_PARAMS = 31, // 31=GSM900, 47=DCS1800, 63=PCS1900
343 RX_AGC_PARAMS_PCS = 63,
344 #if (RF_FAM == 35)
345 RX_PLL_TUNING_TABLE = 65,
346 #endif
347 TX_DATA_BUFFER = 80
348 #if L1_GPRS
349 ,RLC_TX_BUFFER_CS1 = 81,
350 RLC_TX_BUFFER_CS2 = 82,
351 RLC_TX_BUFFER_CS3 = 83,
352 RLC_TX_BUFFER_CS4 = 84
353 #endif
354 };
355
356 enum RX_PARAM
357 {
358 RX_AGC_GAIN = 1,
359 RX_TIMESLOT = 2,
360 RX_AGC_ENA_FLAG = 8,
361 RX_PM_ENABLE = 9,
362 RX_FRONT_DELAY = 10,
363 RX_FLAGS_CAL = 14,
364 RX_FLAGS_PLATFORM = 15,
365 RX_FLAGS_IQ_SWAP = 17,
366 RX_FLAGS_ALL = 18
367 #if L1_GPRS
368 ,RX_GPRS_SLOTS = 28,
369 RX_GPRS_CODING = 29
370 #endif
371 };
372
373 enum TX_PARAM
374 {
375 TX_PWR_LEVEL = 1,
376 TX_APC_DAC = 4,
377 TX_RAMP_TEMPLATE = 5,
378 TX_CHAN_CAL_TABLE = 6,
379 TX_RESERVED = 7,
380 TX_BURST_TYPE = 8,
381 TX_BURST_DATA = 9,
382 TX_TIMING_ADVANCE = 10,
383 TX_TRAINING_SEQ = 11,
384 TX_PWR_SKIP = 13,
385 TX_FLAGS_CAL = 14,
386 TX_FLAGS_PLATFORM = 15,
387 TX_FLAGS_IQ_SWAP = 17,
388 TX_FLAGS_ALL = 18
389 #if L1_GPRS
390 ,TX_GPRS_POWER0 = 20,
391 TX_GPRS_POWER1 = 21,
392 TX_GPRS_POWER2 = 22,
393 TX_GPRS_POWER3 = 23,
394 TX_GPRS_POWER4 = 24,
395 TX_GPRS_POWER5 = 25,
396 TX_GPRS_POWER6 = 26,
397 TX_GPRS_POWER7 = 27,
398 TX_GPRS_SLOTS = 28,
399 TX_GPRS_CODING = 29
400 #endif
401 };
402
403 enum MISC_PARAM
404 {
405 GPIOSTATE0 = 8,
406 GPIODIR0 = 9,
407 GPIOSTATE1 = 10,
408 GPIODIR1 = 11,
409 GPIOSTATE0P = 12,
410 GPIODIR0P = 13,
411 GPIOSTATE1P = 14,
412 GPIODIR1P = 15,
413 ADC_INTERVAL = 18,
414 ADC_ENA_FLAG = 19,
415 CONVERTED_ADC0 = 20,
416 CONVERTED_ADC1 = 21,
417 CONVERTED_ADC2 = 22,
418 CONVERTED_ADC3 = 23,
419 CONVERTED_ADC4 = 24,
420 CONVERTED_ADC5 = 25,
421 CONVERTED_ADC6 = 26,
422 CONVERTED_ADC7 = 27,
423 CONVERTED_ADC8 = 28,
424 RAW_ADC0 = 30,
425 RAW_ADC1 = 31,
426 RAW_ADC2 = 32,
427 RAW_ADC3 = 33,
428 RAW_ADC4 = 34,
429 RAW_ADC5 = 35,
430 RAW_ADC6 = 36,
431 RAW_ADC7 = 37,
432 RAW_ADC8 = 38,
433 ADC0_COEFF_A = 50,
434 ADC1_COEFF_A = 51,
435 ADC2_COEFF_A = 52,
436 ADC3_COEFF_A = 53,
437 ADC4_COEFF_A = 54,
438 ADC5_COEFF_A = 55,
439 ADC6_COEFF_A = 56,
440 ADC7_COEFF_A = 57,
441 ADC8_COEFF_A = 58,
442 ADC0_COEFF_B = 60,
443 ADC1_COEFF_B = 61,
444 ADC2_COEFF_B = 62,
445 ADC3_COEFF_B = 63,
446 ADC4_COEFF_B = 64,
447 ADC5_COEFF_B = 65,
448 ADC6_COEFF_B = 66,
449 ADC7_COEFF_B = 67,
450 ADC8_COEFF_B = 68,
451 SLEEP_MODE = 80,
452 CURRENT_TM_MODE = 127
453 };
454
455 enum STATS_CONFIG
456 {
457 LOOPS = 16,
458 AUTO_RESULT_LOOPS = 17,
459 AUTO_RESET_LOOPS = 18,
460 #if L1_GPRS
461 STAT_GPRS_SLOTS = 20,
462 #endif
463 STAT_TYPE = 24,
464 STAT_BITMASK = 25
465 };
466
467 enum STATS_READ
468 {
469 ACCUMULATED_RX_STATS = 1,
470 MOST_RECENT_RX_STATS = 2
471 };
472
473 enum BITMASK
474 {
475 RSSI = 0x0001,
476 DSP_PM = 0x0002,
477 ANGLE_MEAN = 0x0004,
478 ANGLE_VAR = 0x0008,
479 SNR_MEAN = 0x0010,
480 SNR_VAR = 0x0020,
481 TOA_MEAN = 0x0040,
482 TOA_VAR = 0x0080,
483 RESERVED1 = 0x0100,
484 RESERVED2 = 0x0200,
485 ANGLE_MIN = 0x0400,
486 ANGLE_MAX = 0x0800,
487 FRAME_NUMBER = 0x1000,
488 RUNS = 0x2000,
489 SUCCESSES = 0x4000,
490 BSIC = 0x8000
491 };
492
493 enum RF_ENABLE_E
494 {
495 STOP_ALL = 0,
496 RX_TCH = 1,
497 TX_TCH = 2,
498 RX_TX_TCH = 3,
499 #if L1_GPRS
500 RX_TX_PDTCH = 4,
501 #endif
502 RX_TCH_CONT = 8,
503 TX_TCH_CONT = 9,
504 BCCH_LOOP = 10,
505 SB_LOOP = 11,
506 FB1_LOOP = 12,
507 FB0_LOOP = 13,
508 SINGLE_PM = 15,
509 #if L1_GPRS
510 RX_TX_PDTCH_MON = 16,
511 #endif
512 #if (RF_FAM == 35)
513 RX_PLL_TUNING = 17,
514 #endif
515 RX_TX_MON_TCH = 19,
516 RX_TX_MON = 27
517 };
518
519 enum VERSION_GET_E
520 {
521 BBCHIP_MODULE_REV = 0x10,
522 CHIPID_MODULE_REV = 0x14,
523 CHIPVER_MODULE_REV = 0x15,
524 DSPSW_MODULE_REV = 0x22,
525 ANALOGCHIP_MODULE_REV = 0x30,
526 GSM_MODULE_REV = 0x80,
527 LAYER1_MODULE_REV = 0x84,
528 RFDRIVER_MODULE_REV = 0x88,
529 TM_API_MODULE_REV = 0xE0,
530 L1_TM_CORE_MODULE_REV = 0xE1,
531 STD_MODULE_REV = 0xE2,
532 DSP_MODULE_REV = 0xE3,
533 BOARD_MODULE_REV = 0xE4,
534 RF_MODULE_REV = 0xE5
535 };
536