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comparison chipsetsw/layer1/tpu_drivers/source0/tpudrv2.h @ 0:509db1a7b7b8

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initial import: leo2moko-r1
author Space Falcon <falcon@ivan.Harhan.ORG>
date Mon, 01 Jun 2015 03:24:05 +0000
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-1:000000000000 0:509db1a7b7b8
1 /****************** Revision Controle System Header ***********************
2 * GSM Layer 1 software
3 * Copyright (c) Texas Instruments 1998
4 *
5 * Filename tpudrv2.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ****************** Revision Controle System Header ***********************/
9
10 /***********************************************************/
11 /* */
12 /* Used Timing definitions given in "L1_TIME.H" */
13 /* -------------------------------------------- */
14 /* */
15 /* START_RX_FB STOP_RX_FB */
16 /* START_RX_SB STOP_RX_SB */
17 /* START_RX_SNB STOP_RX_SNB */
18 /* START_RX_NNB STOP_RX_NNB */
19 /* START_RX_PW_1 STOP_RX_PW_1 */
20 /* START_RX_FB26 STOP_RX_FB26 */
21 /* START_TX_NB STOP_TX_NB */
22 /* START_RX_RA STOP_RX_RA */
23 /* */
24 /***********************************************************/
25
26 // BB Timings
27 #define VG_CAL_RX_DELAY 65
28 #define VG_CAL_TX_DELAY 143
29 #define VG_BDLON_DELAY 70
30 #define VG_BULOFF_DELAY 35
31 #define VG_BULON_DELAY 159
32
33 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
34 #define OM_CAL_RX_DELAY 65
35 #define OM_CAL_TX_DELAY 230
36 #define OM_BDLON_DELAY 166
37 #define OM_BULOFF_DELAY 35
38 #define OM_BULON_DELAY 250
39
40 #define SL_SU_DELAY1 4
41 #define SL_SU_DELAY2 3
42 #endif
43
44 #define RA_TRANSMIS_DURATION ( RA_BURST_DURATION + 46L )
45 #define NB_TRANSMIS_DURATION ( NB_BURST_DURATION_UL + 29L )
46 #define START_TX_NB ( 4984L ) // Calibration time is reduced of 4 GSM bit due to a slow APC ramp
47 #define STOP_TX_NB ( START_TX_NB + NB_TRANSMIS_DURATION )
48 #define STOP_TX_RA ( START_TX_RA + RA_TRANSMIS_DURATION )
49
50
51 #ifdef TPUDRV2_C
52
53 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
54 const unsigned short RF_Sleep[] ={
55 /*** Immediate ***/
56 TPU_MOVE(TSP_SPI_SET1, TSP_ENA_POS_MSB),
57 TPU_MOVE(TSP_SPI_SET2, TSP_ENA_POS_MSB | TSP_ENA_POS),
58 0
59 };
60
61 const unsigned short RF_Wakeup[] ={
62 /*** Immediate ***/
63 TPU_MOVE(TSP_SPI_SET1, 0x00),
64 TPU_MOVE(TSP_SPI_SET2, TSP_ENA_POS),
65 0
66 };
67
68
69 /*--------------------------------------------------------------------------------------------------------------*/
70 /* Serial link delay for OMEGA. this delay includes */
71 /* TSP register programming and serialization of data to OMEGA */
72 /* */
73 /* */
74 /* 4991 4992 4993 4994 4995 4996 4997 */
75 /* ---------------------------------------------------------------------------------------------- */
76 /* | | | | | | | */
77 /*OMEGA | AT(4991) | Clock conf | Nb of bit | Load data | Send write | Serialization */
78 /* | | | to shift | to shift | command | | */
79 /* ---------------------------------------------------------------------------------------------- */
80 /* | | | | | | | */
81 /* VEGA | | | | | | AT(4996) | TSPACT */
82 /* | | | | | | | */
83 /* ------------------------------------------------------------------------------------------|--- */
84 /* <------------------------------------------------------------------> | */
85 /* SL_SU_DELAY1 | */
86 /* V */
87 /* ACTION ON WINDOW */
88 /* */
89 /* When the TSP port is already configured is not necessary to configure the clock and the number of bits */
90 /* */
91 /* */
92 /* 4998 4999 0 1 2 */
93 /* ------------------------------------------------------------------- */
94 /* | | | | | | */
95 /*OMEGA | AT(4998) | Load data | Send write | Serialization | */
96 /* | | to shift | command | | | */
97 /* ---------------------------------------------------------------------- */
98 /* | | | | | | */
99 /* VEGA | | | | AT(4996) | TSPACT */
100 /* | | | | | | */
101 /* ------------------------------------------------------------|------- */
102 /* <---------------------------------------> | */
103 /* SL_SU_DELAY2 | */
104 /* V */
105 /* ACTION ON WINDOW */
106 /* */
107 /* */
108 /* NOTE : WITH THIS IMPLEMENTATION THE OMEGA SCENARIO ANTICIPATES THE ACTION ON WINDOW SIGNAL OF 347 ns. */
109 /* ANYWAY ACTION IS TAKEN IN THE SAME QB INTERVAL */
110 /* */
111 /* */
112 /*--------------------------------------------------------------------------------------------------------------*/
113
114
115
116 /***********************************************************/
117 /* BASEBAND TPU SCENARIOS FOR OMEGA */
118 /***********************************************************/
119
120 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
121 // Samson TPU scenario: add 1 bit to reception window for DMA thres = 2
122 const SYS_UWORD16 VG_DlNormalBurst [] = {
123
124 TPU_AT (START_RX_SNB -VG_BDLON_DELAY - SL_SU_DELAY1 ), // AT(4991)
125 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE),
126 TPU_MOVE (TSP_CTRL1,6),
127 TPU_MOVE (TSP_TX_REG_1,BDLON),
128 TPU_MOVE (TSP_CTRL2, TC2_WR),
129
130
131 TPU_AT (START_RX_SNB - VG_CAL_RX_DELAY - SL_SU_DELAY2), // AT(4998)
132 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL),
133 TPU_MOVE (TSP_CTRL2, TC2_WR),
134
135 TPU_AT (START_RX_SNB - SL_SU_DELAY2), // AT(63)
136 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA),
137 TPU_MOVE (TSP_CTRL2, TC2_WR),
138
139 TPU_AT (STOP_RX_SNB - SL_SU_DELAY2), // AT(699)
140 TPU_MOVE (TSP_TX_REG_1,0x00),
141 TPU_MOVE (TSP_CTRL2, TC2_WR),
142
143 0
144 };
145
146
147 // HERCULES TPU scenario
148 const SYS_UWORD16 VG_DlFrequencyBurstIdle [] = {
149
150 TPU_AT (START_RX_FB - VG_BDLON_DELAY -SL_SU_DELAY1 ), // AT(4991)
151 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE),
152 TPU_MOVE (TSP_CTRL1,6),
153 TPU_MOVE (TSP_TX_REG_1,BDLON),
154 TPU_MOVE (TSP_CTRL2, TC2_WR),
155
156
157 TPU_AT (START_RX_FB - VG_CAL_RX_DELAY -SL_SU_DELAY2), // AT(4998)
158 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL),
159 TPU_MOVE (TSP_CTRL2, TC2_WR),
160
161
162 TPU_AT (START_RX_FB - SL_SU_DELAY2), // AT(63)
163 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA),
164 TPU_MOVE (TSP_CTRL2, TC2_WR),
165
166 TPU_AT (0),
167 TPU_AT (0),
168 TPU_AT (0),
169 TPU_AT (0),
170 TPU_AT (0),
171 TPU_AT (0),
172 TPU_AT (0),
173 TPU_AT (0),
174 TPU_AT (0),
175 TPU_AT (0),
176 TPU_AT (0),
177
178 TPU_AT (STOP_RX_FB - SL_SU_DELAY2), // AT(2119)
179 TPU_MOVE (TSP_TX_REG_1,0X00),
180 TPU_MOVE (TSP_CTRL2, TC2_WR),
181
182 0
183 };
184
185
186 #else
187 /* HERCULES TPU scenario */
188
189 const SYS_UWORD16 VG_DlNormalBurst [] = {
190
191 TPU_AT (START_RX_SNB -VG_BDLON_DELAY - SL_SU_DELAY1 ), // AT(4991)
192 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE),
193 TPU_MOVE (TSP_CTRL1,6),
194 TPU_MOVE (TSP_TX_REG_1,BDLON),
195 TPU_MOVE (TSP_CTRL2, TC2_WR),
196
197
198 TPU_AT (START_RX_SNB - VG_CAL_RX_DELAY - SL_SU_DELAY2), // AT(4998)
199 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL),
200 TPU_MOVE (TSP_CTRL2, TC2_WR),
201
202 TPU_AT (START_RX_SNB - SL_SU_DELAY2), // AT(63)
203 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA),
204 TPU_MOVE (TSP_CTRL2, TC2_WR),
205
206 TPU_AT (STOP_RX_SNB - SL_SU_DELAY2), // AT(699)
207 TPU_MOVE (TSP_TX_REG_1,0x00),
208 TPU_MOVE (TSP_CTRL2, TC2_WR),
209
210 0
211 };
212
213
214 // HERCULES TPU scenario
215 const SYS_UWORD16 VG_DlFrequencyBurstIdle [] = {
216
217 TPU_AT (START_RX_FB - VG_BDLON_DELAY -SL_SU_DELAY1 ), // AT(4991)
218 // TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE),
219 TPU_MOVE (TSP_CTRL1,6),
220 TPU_MOVE (TSP_TX_REG_1,BDLON),
221 TPU_MOVE (TSP_CTRL2, TC2_WR),
222
223
224 TPU_AT (START_RX_FB - VG_CAL_RX_DELAY -SL_SU_DELAY2), // AT(4998)
225 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL),
226 TPU_MOVE (TSP_CTRL2, TC2_WR),
227
228
229 TPU_AT (START_RX_FB - SL_SU_DELAY2), // AT(63)
230 TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA),
231 TPU_MOVE (TSP_CTRL2, TC2_WR),
232
233 TPU_AT (0),
234 TPU_AT (0),
235 TPU_AT (0),
236 TPU_AT (0),
237 TPU_AT (0),
238 TPU_AT (0),
239 TPU_AT (0),
240 TPU_AT (0),
241 TPU_AT (0),
242 TPU_AT (0),
243 TPU_AT (0),
244
245 TPU_AT (STOP_RX_FB - SL_SU_DELAY2), // AT(2119)
246 TPU_MOVE (TSP_TX_REG_1,0X00),
247 TPU_MOVE (TSP_CTRL2, TC2_WR),
248
249 0
250 };
251
252
253
254 #endif
255
256
257
258 // HERCULES TPU scenario for Omega windows reset
259 const SYS_UWORD16 VG_Omega_win_reset[] = {
260
261 TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE),
262 TPU_MOVE (TSP_CTRL1,6),
263 TPU_MOVE (TSP_TX_REG_1,0x00),
264 TPU_MOVE (TSP_CTRL2, TC2_WR),
265 0
266 };
267
268 #endif
269
270 #else
271 extern const SYS_UWORD16 VG_DlNormalBurst[];
272 extern const SYS_UWORD16 VG_DlFrequencyBurstIdle[];
273 #endif
274